ST STM32L4+ Series Reference Manual page 2287

RM0432
Date
05-Mar-2018
Table 441. Document revision history (continued)
Revision
Added:
– Section 22.3: DAC implementation
Updated:
– Section 1.2: List of abbreviations for registers
– Section 11: Direct memory access controller (DMA)
subsections contents
– Section 22.7: DAC
subsections
– Section 22.7.1: DAC control register (DAC_CR)
– Section 18.7.6: NOR/PSRAM controller registers
– Section 18.8.7: NAND Flash controller registers
– Table 118: FMC register map and reset values
– Section 29.8: LTDC
format of all subsections
– Section 51.6.7: LPUART interrupt and status register [alternate]
3
(LPUART_ISR)
– Section 51.6.9: LPUART interrupt flag clear register
(LPUART_ICR)
– Table 364: LPUART register map and reset values
– Section 56.8.1: Host SOFs
– Section 56.8.2: Peripheral SOFs
– Section 56.11.3: FIFO RAM allocation
– Section 56.15: OTG_FS
subsections
Deleted:
– From Section 12: DMA request multiplexer
size identification register (DMAMUX_SIDR), DMAMUX IP
identification register (DMAMUX_IPIDR), DMAMUX version
register (DMAMUX_VERR), DMAMUX hardware configuration 1
register (DMAMUX_HWCFGR1) and DMAMUX hardware
configuration 2 register (DMAMUX_HWCFGR2)
RM0432 Rev 6
Changes
registers: naming conventions of all
registers: naming conventions and reset value
registers: naming conventions of all
(DMAMUX): DMAMUX
Revision history
and all
2287/2301
2292