ST STM32L4+ Series Reference Manual page 2288

Revision history
Date
03-May-2018
01-Feb-2019
2288/2301
Table 441. Document revision history (continued)
Revision
Added:
– Section 1.1: General information
– Section 5.1.7: VDD12 domain
regulator overview
– Section Table 8.: Flash module - 1 Mbyte dual-bank organization
(64 bits read width)
– Section Table 9.: Flash module - 1 Mbyte single-bank organization
(128 bits read width)
Updated:
– Section 3.3.1: Flash memory organization
– Section 5.1.8: Dynamic voltage scaling management
– DB1M bit description on
and Section 3.7.8: Flash option register (FLASH_OPTR)
– Figure 454
block diagram
– Section 8.4: GPIO
subsections
– Figure 158: Dual-channel DAC block diagram
– Section 22: Digital-to-analog converter (DAC)
4
of all subsections
– Section 22.4.1: DAC block diagram
– Section 22.4.8: DAC noise generation
– Section 22.4.9: DAC triangle-wave generation
– Section Table 147.: Sample and refresh timings
– Section : Example of the sample and refresh time calculation with
output buffer on on page 736
– Section 53.6: SAI registers
– Figure 54: Secure digital input/output MultiMediaCard interface
(SDMMC)
– Figure 573: SDMMC block diagram
– Table 385: SDMMC internal input/output signals
– Table 386: SDMMC pins
– Figure 54.5.3: General description
– Table 387: SDMMC Command and data phase selection
– Table 387: SDMMC Command and data phase selection
– Figure 575: Control unit
– Table 404: CMD12 use cases
Updated:
– Table 8: Flash module - 1 Mbyte dual-bank organization (64 bits
read width).
– Figure 3: Memory map for STM32L4Rxxx and
– Section 3.3.1: Flash memory
5
– Address offset of
register (FLASH_WRP2AR)
B address register (FLASH_WRP1BR)
– Section 57.6.1: MCU device ID
– Section 58.3: Package data
RM0432 Rev 6
Changes
including
Section 3.4.1: Option bytes description
was moved to the created
registers: naming conventions of all
was fully restructured
naming conventions of all subsections
organization.
Section 3.7.12: Flash WRP2 area A address
and Section 3.7.15: Flash WRP1 area
code.
register.
RM0432
Figure 11: Internal main
Section 45.3.1: WWDG
naming conventions
STM32L4Sxxx.