Figure 5. Sequential 32-Bit Instruction Execution - ST STM32F405 Reference Manual

RM0090
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.

Figure 5. Sequential 32-bit instruction execution

@ F D
WAIT
1 1 1
@ F
2 2
@
3
ins 1 ins 2
fetch fetch
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4
@ F D
Wait data
1 1 1
@ F
2 2
@
3
ins 1 ins 2
fetch fetch
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4
Read ins 5, 6, 7, 8
RM0090 Rev 18
Embedded Flash memory interface
E
1
D E
2 2
F D E
3 3 3
@ F D E
4 4 4 4
@ F
WAIT
5 5
@
6
ins 3 ins 4 ins 5
fetch fetch
fetch
Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8
E
1
D E
2 2
F D E
3 3 3
@ F D E
4 4 4 4
@ F D E
5 5 5 5
@ F D E
6 6 6
@ F D
7 7 7
@ F
8 8
ins 3 ins 4 ins 5 ins 6 ins 7
fetch fetch fetch fetch fetch
Gives ins 5, 6, 7, 8
Read ins 9, 10, ...
Without prefetch
D E
5 5
F D E
6 6 6
@ F D
7 7 7
@ F
8 8
ins 6 ins 7 ins 8
fetch fetch fetch
With prefetch
Cortex-M4 pipeline
@
F D
AHB protocol
ins 8
fetch
@ : address requested
F: Fetch stage
D: Decode stage
E: Execute stage
E
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