Rcc Plli2S Configuration Register (Rcc_Plli2Scfgr) - ST STM32F405 Reference Manual

RM0090
Bits 29:28 Reserved, must be kept at reset value.
Bits 27:13 INCSTEP: Incrementation step
Bits 12:0 MODPER: Modulation period
6.3.23

RCC PLLI2S configuration register (RCC_PLLI2SCFGR)

Address offset: 0x84
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLI2S clock outputs according to the formulas:
f
(VCO clock)
f
(PLL I2S clock output)
31 30 29
PLLI2S PLLI2S
Reserv
R2 R1
ed
rw rw
15 14 13
PLLI2SN PLLI2SN
Reserv
8 7
ed
rw rw
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
These bits are set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile amplitude.
These bits are set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile period.
= f
(PLLI2S clock input)
= f
(VCO clock)
28 27 26
PLLI2S
PLLI2SQ
R0
rw rw rw
12 11 10
PLLI2SN PLLI2SN PLLI2SN
6 5 4
rw rw rw
× (PLLI2SN / PLLM)
/ PLLI2SR
25 24 23
rw rw
9 8 7
PLLI2SN PLLI2SN PLLI2SN
3 2 1
rw rw rw
RM0090 Rev 18
22 21 20 19
Reserved
6 5 4 3
PLLI2SN
0
Reserved
rw
18 17 16
2 1 0
203/1749
212