ST ST32M103 Series Reference Manual
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ST ST32M103 Series Reference Manual

Advanced arm-based 32-bit mcus
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Table of Contents

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Introduction
This Reference Manual targets application developers. It provides complete information on
how to use the STM32F101xx and ST32M103xx microcontroller memory and peripherals.
The STM32F101xx and ST32M103xx will be referred to as STM32F10x throughout the
document.
The STM32F10x is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
STM32F101xx and ST32M103xx datasheets.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10x Flash Programming Manual.
For information on the ARM Cortex-M3 core, please refer to the Cortex-M3
Reference Manual.
Related documents
Available from www.arm.com:
Cortex-M3
Available from www.st.com:
STM32F101xx ST32M103xx datasheets
STM32F10x Flash Programming Manual
June 2007
www.BDTIC.com/ST
advanced ARM-based 32-bit MCUs
TM
Technical Reference Manual
Rev 1
Reference manual
STM32F101xx and STM32F103xx
UM0306
TM
Technical
1/519
www.st.com

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Summary of Contents for ST ST32M103 Series

  • Page 1 For information on the ARM Cortex-M3 core, please refer to the Cortex-M3 Technical Reference Manual. Related documents Available from www.arm.com: Cortex-M3 Technical Reference Manual Available from www.st.com: STM32F101xx ST32M103xx datasheets STM32F10x Flash Programming Manual June 2007 Rev 1 1/519 www.st.com...

  • Page 2: Table Of Contents

    PWR register map ......... . 44 2/519 www.BDTIC.com/ST...
  • Page 3 Alternate functions (AF) ........75 5.1.5 Software remapping of I/O alternate functions ....76 3/519 www.BDTIC.com/ST...
  • Page 4 Interrupt and exception vectors ....... 98 External interrupt/event controller (EXTI) ......101 4/519 www.BDTIC.com/ST...
  • Page 5 RTC register description ........125 5/519 www.BDTIC.com/ST...
  • Page 6 Functional description ........145 6/519 www.BDTIC.com/ST...
  • Page 7 TIM1 register description ........191 12.5.1 Control register 1 (TIM1_CR1) ......191 7/519 www.BDTIC.com/ST...
  • Page 8 13.4.10 One pulse mode ......... 242 13.4.11 Clearing the OCxREF signal on an external event ....244 8/519 www.BDTIC.com/ST...
  • Page 9 Operating modes ......... . 285 9/519 www.BDTIC.com/ST...
  • Page 10 Interrupt requests ......... . 344 10/519 www.BDTIC.com/ST...
  • Page 11 SPI register map ......... . . 376 Universal synchronous asynchronous receiver transmitter (USART) . . 11/519 www.BDTIC.com/ST...
  • Page 12 System and power-on reset ....... . . 422 12/519 www.BDTIC.com/ST...
  • Page 13 19.10.6 Independent mode ........467 13/519 www.BDTIC.com/ST...
  • Page 14 TMC TAP ..........494 14/519 www.BDTIC.com/ST...
  • Page 15 20.17 DBG register map ......... . 513 15/519 www.BDTIC.com/ST...
  • Page 16 Revision history ......... . 514 16/519 www.BDTIC.com/ST...
  • Page 17 SPI interrupt requests ........... . 369 17/519 www.BDTIC.com/ST...
  • Page 18 Document revision history ..........514 18/519 www.BDTIC.com/ST...
  • Page 19 External trigger input block ..........165 19/519 www.BDTIC.com/ST...
  • Page 20 Figure 100. PWM input mode timing........... 238 20/519 www.BDTIC.com/ST...
  • Page 21 Figure 152. USART example of synchronous transmission....... . . 396 21/519 www.BDTIC.com/ST...
  • Page 22 Figure 185. JTAG TAP connections ..........493 22/519 www.BDTIC.com/ST...

  • Page 23: Documentation Conventions

    Software can read as well as set this bit. Writing ‘0’ has no effect on the bit read/set (rs) value. toggle (t) The software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. 23/519 www.BDTIC.com/ST...

  • Page 24: Memory And Bus Architecture

    This bus connects the DCode bus (literal load and debug access) of the Cortex-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA. 24/519 www.BDTIC.com/ST...

  • Page 25: Memory Organization

    The addressable memory space is divided into 8 main blocks, each of 512MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved” (gray shaded areas in the Figure 2 on page 26). 25/519 www.BDTIC.com/ST...

  • Page 26: Memory Map

    USART2 0x4000 4400 CODE 0x0800 0000 reserved 0x0000 0000 0x4000 3C00 SPI2 0x4000 3800 reserved 0x4000 3400 IWDG 0x4000 3000 WWDG Reserved 0x4000 2C00 0x4000 2800 reserved 0x4000 0C00 TIM4 0x4000 0800 TIM3 0x4000 0400 TIM2 0x4000 0000 26/519 www.BDTIC.com/ST...

  • Page 27: Peripheral Memory Map

    0X4001 0C00 - 0x4001 0FFF GPIO Port B Section 5.5.1 on page 0x4001 0800 - 0x4001 0BFF GPIO Port A Section 6.2 on page 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO Section 5.5 on page 97 27/519 www.BDTIC.com/ST...

  • Page 28: Embedded Sram

    0x4000 0000 - 0x4000 03FF TIM2 timer 2.3.2 Embedded SRAM The STM32F10x features 20 KBytes of static SRAM. It can be accessed as bytes, half- words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000. 28/519 www.BDTIC.com/ST...

  • Page 29: Bit Banding

    Information block of size 320 * 64 bits. Each information block is divided into 2 pages or 2Kbyte and 0.5Kbyte (seeTable The Flash memory interface features: Read interface with prefetch buffer (2x64-bit words) Option byte Loader Flash Program / Erase operation Access / Write Protection 29/519 www.BDTIC.com/ST...

  • Page 30: Table 2. Flash Module Organization

    0x4002 2018 - 0x4002 201B FLASH_OBR 0x4002 201C - 0x4002 201F FLASH_WRPR 0x4002 2020 - 0x4002 2023 Reserved 0x4002 2024 - 0x4002 2087 Note: For further information on the Flash memory registers, please refer to the STM32F10x Flash Programming manual. 30/519 www.BDTIC.com/ST...
  • Page 31 The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI. 31/519 www.BDTIC.com/ST...

  • Page 32: Boot Configuration

    Even when aliased in the boot memory space, the related memory (Flash memory or SRAM) is still accessible at its original memory space. After this startup delay has elapsed, the CPU starts code execution from the boot memory, located at the bottom of the memory address space starting from 0x0000_0000h. 32/519 www.BDTIC.com/ST...

  • Page 33: Power Control (Pwr)

    V . The voltage on V can range from 0V REF+ REF- REF+ to V On packages with 64 pins or less: The ADC voltage supply and ground are internally tied to the ADC reference voltage pins. 33/519 www.BDTIC.com/ST...

  • Page 34: Battery Backup

    The device remains in Reset mode when V is below a specified threshold, V POR/PDR without the need for an external reset circuit. For more details concerning the Power On/Power Down Reset threshold, refer to the electrical characteristics of the datasheet. 34/519 www.BDTIC.com/ST...

  • Page 35: Programmable Voltage Detector (Pvd)

    PVD threshold and/or when V rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. Figure 5. PVD thresholds 100 mV PVD Threshold hysteresis PVD Output 35/519 www.BDTIC.com/ST...

  • Page 36: Low-Power Modes

    In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 4.3.2: Clock configuration register (RCC_CFGR). 36/519 www.BDTIC.com/ST...

  • Page 37: Peripheral Clock Gating

    Refer to the Cortex-M3 System Control register. If WFI was used for entry: Interrupt: Refer to Table 27: Vector table Mode Exit If WFE was used for entry Wake-up event: Refer to Section 6.2.3: Wake-up event management Wake-up latency None 37/519 www.BDTIC.com/ST...

  • Page 38: Stop Mode

    When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from STOP mode. By keeping the internal regulator ON during STOP mode, the consumption is higher although the startup time is reduced. 38/519 www.BDTIC.com/ST...

  • Page 39: Standby Mode

    After waking up from STANDBY mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power control/status register (PWR_CSR) indicates that the MCU was in STANDBY mode. 39/519 www.BDTIC.com/ST...

  • Page 40: Auto-Wake-Up (Awu) From Low-Power Mode

    To wake-up from STOP mode with an RTC alarm event, it is necessary to: Configure the EXTI Line 17 to be sensitive to rising edge Configure the RTC to generate the RTC alarm To wake-up from STANDBY mode, there is no need to configure the EXTI Line 17. 40/519 www.BDTIC.com/ST...

  • Page 41: Power Control Registers

    0: No effect 1: Clear the SBF Standby Flag (write). CWUF: Clear Wake-up Flag. This bit is always read as 0. Bit 2 0: No effect 1: Clear the WUF Wake-up Flag after 2 System clock cycles. (write) 41/519 www.BDTIC.com/ST...
  • Page 42 1: Enter STANDBY mode when the CPU enters Deepsleep. LPDS: Low-Power Deepsleep. This bit is set and cleared by software. It works together with the PDDS bit. 0: Bit 0 Voltage regulator on during STOP mode 1: Voltage regulator in low-power mode during STOP mode 42/519 www.BDTIC.com/ST...

  • Page 43: Power Control/Status Register (Pwr_Csr)

    This bit is set by hardware and cleared only by a POR/PDR (Power On Reset/Power Down Reset) or by setting the CWUF bit in the Power control Bit 0 register (PWR_CR) 0: No wake-up event occurred 1: A wake-up event was received from the WKUP pin or from the RTC alarm 43/519 www.BDTIC.com/ST...

  • Page 44: Pwr Register Map

    The following table summarizes the PWR registers. Table 9. PWR - register map and reset values Offset Register PWR_CR PLS[2:0] 000h Reserved Reset Value PWR_CSR 004h Reserved Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 44/519 www.BDTIC.com/ST...

  • Page 45: Reset And Clock Control (Rcc)

    This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a STOP mode entry sequence is successfully executed, the device is reset instead of entering STOP mode. For further information on the User Option Bytes, refer to the STM32F10x Flash Programming Manual. 45/519 www.BDTIC.com/ST...

  • Page 46: Power Reset

    32 kHz Low Speed Internal RC (LSI RC) which drives the Independent Watchdog and optionally the RTC used for Auto Wake-up from STOP/STANDBY mode. 32.768 kHz Low Speed External crystal (LSE crystal) which optionally drives the Real- Time Clock (RTCCLK) 46/519 www.BDTIC.com/ST...

  • Page 47: Figure 7. Clock Tree

    8. The SysTick can work either with this clock or with the Cortex clock (AHB), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. 47/519 www.BDTIC.com/ST...

  • Page 48: Hse Clock

    MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 48/519 www.BDTIC.com/ST...

  • Page 49: Hsi Clock

    Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After Reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...

  • Page 50: Lse Clock

    (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock. 50/519 www.BDTIC.com/ST...

  • Page 51: Clock Security System (Css)

    IWDG. 4.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be 51/519 www.BDTIC.com/ST...

  • Page 52: Rcc Register Description

    Bits 23:20 Reserved, always read as 0. CSSON Clock Security System enable Set and reset by software to enable clock detector. Bit 19 0: Clock detector OFF 1: Clock detector ON if external 1-25 MHz oscillator is ready. 52/519 www.BDTIC.com/ST...
  • Page 53 This bit can not be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: internal 8 MHz RC oscillator OFF 1: internal 8 MHz RC oscillator ON 53/519 www.BDTIC.com/ST...

  • Page 54: Clock Configuration Register (Rcc_Cfgr)

    Set and reset by software to generate 48 MHz USB clock. This bit must be valid before enabling the USB clock in the RCC_APB1ENR register. This bit can’t be Bit 22 reset if the USB clock is enabled. 0: PLL clock is divided by 1.5 1: PLL clock is not divided 54/519 www.BDTIC.com/ST...
  • Page 55 Set and reset by software to control APB High speed clocks division factor. 0xx: HCLK not divided Bits 13:11 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 55/519 www.BDTIC.com/ST...
  • Page 56 HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). Bits 1:0 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: not allowed 56/519 www.BDTIC.com/ST...

  • Page 57: Clock Interrupt Register (Rcc_Cir)

    Reset by hardware when clear done. 0: HSIRDYF not cleared 1: HSIRDYF cleared LSERDYC LSE Ready Interrupt Clear Set by software to clear LSERDYF. Bit 17 Reset by hardware when clear done. 0: LSERDYF not cleared 1: LSERDYF cleared 57/519 www.BDTIC.com/ST...
  • Page 58 Set by hardware when External Low Speed clock becomes stable and Bit3 HSERDYDIE is set. 0: No clock ready interrupt caused by the external 1-25 MHz oscillator 1: Clock ready interrupt caused by the external 1-25 MHz oscillator 58/519 www.BDTIC.com/ST...
  • Page 59 Set by hardware when Internal Low Speed clock becomes stable and LSIRDYDIE Bit 0 is set. 0: No clock ready interrupt caused by the internal RC 32 kHz oscillator 1: Clock ready interrupt caused by the internal RC 32 kHz oscillator 59/519 www.BDTIC.com/ST...

  • Page 60: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)

    Set and reset by software. Bit 9 0: No effect 1: Reset ADC 1 interface Bits 8:7 Reserved, always read as 0. IOPERST IO port E reset Set and reset by software. Bit 6 0: No effect 1: Reset IO port E 60/519 www.BDTIC.com/ST...
  • Page 61 Set and reset by software. Bit 2 0: No effect 1: Reset I/O port A Bit 1 Reserved, always read as 0. AFIORST Alternate Function I/O reset Set and reset by software. Bit 0 0: No effect 1: Reset Alternate Function 61/519 www.BDTIC.com/ST...

  • Page 62: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)

    1: Reset USB I2C2RST I2C 2 reset Set and reset by software. Bit 22 0: No effect 1: Reset I2C 2 I2C1RST I2C 1 reset Set and reset by software. Bit 21 0: No effect 1: Reset I2C 1 62/519 www.BDTIC.com/ST...
  • Page 63 1: Reset timer 4 TIM3RST Timer 3 reset Set and reset by software. Bit 1 0: No effect 1: Reset timer 3 TIM2RST Timer 2 reset Set and reset by software. Bit 0 0: No effect 1: Reset timer 2 63/519 www.BDTIC.com/ST...

  • Page 64: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)

    0: SRAM interface clock disabled during SLEEP mode. 1: SRAM interface clock enabled during SLEEP mode Bit 1 Reserved, always read as 0. DMAEN DMA clock enable Set and reset by software. Bit 0 0: DMA clock disabled 1: DMA clock enabled 64/519 www.BDTIC.com/ST...

  • Page 65: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)

    0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled ADC1EN ADC 1 interface clock enable Set and reset by software. Bit 9 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bits 8:7 Reserved, always read as 0. 65/519 www.BDTIC.com/ST...
  • Page 66 0: I/O port A clock disabled 1:I/O port A clock enabled Bit 1 Reserved, always read as 0. AFIOEN Alternate Function I/O clock enable Set and reset by software. Bit 0 0: Alternate Function I/O clock disabled 1:Alternate Function I/O clock enabled 66/519 www.BDTIC.com/ST...

  • Page 67: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)

    USBEN USB clock enable Set and reset by software. Bit 23 0: USB clock disabled 1: USB clock enabled I2C2EN I2C 2 clock enable Set and reset by software. Bit 22 0: I2C 2 clock disabled 1: I2C 2 clock enabled 67/519 www.BDTIC.com/ST...
  • Page 68 Set and reset by software. Bit 1 0: Timer 3 clock disabled 1: Timer 3 clock enabled TIM2EN Timer 2 clock enable Set and reset by software. Bit 0 0: Timer 2 clock disabled 1: Timer 2 clock enabled 68/519 www.BDTIC.com/ST...

  • Page 69: Backup Domain Control Register (Rcc_Bdcr)

    LSEBYP External Low Speed oscillator Bypass Set and reset by software to bypass oscillator in debug mode. This bit can be Bit 2 written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed 69/519 www.BDTIC.com/ST...

  • Page 70: Control/Status Register (Rcc_Csr)

    1: Window watchdog reset occurred IWDGRSTF Independent Watchdog reset flag Reset by software by writing the RMVF bit. Bit 29 Set by hardware when a watchdog reset from V domain occurs. 0: No watchdog reset occurred 1: Watchdog reset occurred 70/519 www.BDTIC.com/ST...
  • Page 71 0: Internal RC 32 kHz oscillator not ready 1: Internal RC 32 kHz oscillator ready LSION Internal Low Speed oscillator enable Set and reset by software. Bit 0 0: Internal RC 32 kHz oscillator OFF 1: Internal RC 32 kHz oscillator ON 71/519 www.BDTIC.com/ST...

  • Page 72: Rcc Register Map

    Reset Value RCC_APB2ENR 018h Reserved Reset Value RCC_APB1ENR 01Ch Reserved Reserved Reset Value RCC_BDCR 020h Reserved Reserved Reserved [1:0] Reset Value RCC_CSR 024h Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 72/519 www.BDTIC.com/ST...

  • Page 73: General Purpose And Alternate Function I/O (Gpio And Afio)

    GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access. Figure 9 shows the basic structure of an I/O Port bit. 73/519 www.BDTIC.com/ST...

  • Page 74: General Purpose I/O (Gpio)

    Max. output speed 2 MHz Max. output speed 50 MHz 5.1.1 General purpose I/O (GPIO) During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode (CNFx[1:0]=01b, MODE[1:0]=00b). 74/519 www.BDTIC.com/ST...

  • Page 75: Atomic Bit Set Or Bit Reset

    If you configure a port bit as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral. If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified. 75/519 www.BDTIC.com/ST...

  • Page 76: Software Remapping Of I/O Alternate Functions

    Input Configuration of the I/O Port bit. Figure 10. Input floating/pull up/pull down configurations DD_IO ON/OFF PULL READ DD_IO TTL SCHMITT PULL ON/OFF PROTECTION TRIGGER DOWN DIODE WRITE INPUT DRIVER I/O PIN OUTPUT DRIVER PROTECTION DIODE READ/WRITE 76/519 www.BDTIC.com/ST...

  • Page 77: Output Configuration

    A read access to the Output Data register gets the last written value in Push-Pull mode Figure 12 on page 78 shows the Alternate Function Configuration of the I/O Port bit. Also, refer to Section 5.4: AFIO register description on page 91 for further information. 77/519 www.BDTIC.com/ST...

  • Page 78: Analog Input Configuration

    I/O pin. The output of the Schmitt Trigger is forced to a constant value (0). The weak pull-up and pull-down resistors are disabled. Read access to the Input Data Register gets the value “0”. Figure 13 on page 79 shows the High impedance-Analog Input Configuration of the I/O Port bit. 78/519 www.BDTIC.com/ST...

  • Page 79: Figure 13. High Impedance-Analog Input Configuration

    General purpose and alternate function I/O (GPIO and AFIO) Figure 13. High impedance-analog input configuration Analog Input TO ON-CHIP PERIPHERAL READ VDD_IO TTL SCHMITT PROTECTION TRIGGER DIODE WRITE INPUT DRIVER I/O PIN PROTECTION DIODE READ/WRITE FROM ON-CHIP PERIPHERAL 79/519 www.BDTIC.com/ST...

  • Page 80: Gpio Register Description

    Table 11: Port bit configuration table on page Bits 29:28, 25:24, 21:20, 17:16, 00: Input mode (reset state) 13:12, 9:8, 5:4, 1:0 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz. 80/519 www.BDTIC.com/ST...

  • Page 81: Port Configuration Register High (Gpiox_Crh) (X=A..e

    Table 11: Port bit configuration table on page Bits 29:28, 25:24, 21:20, 17:16, 00: Input mode (reset state) 13:12, 9:8, 5:4, 1:0 01: Output mode, max speed 2 MHz. 10: Output mode, max speed 10 MHz. 11: Output mode, max speed 50 MHz. 81/519 www.BDTIC.com/ST...

  • Page 82: Port Input Data Register (Gpiox_Idr) (X=A..e

    Reserved, always read as 0. IDRx[15:0]: Port input data (x= 0 .. 15) Bits 31:0 These bits are read only and can be accessed in Word mode only. They contain the input value of the corresponding I/O port. 82/519 www.BDTIC.com/ST...

  • Page 83: Port Output Data Register (Gpiox_Odr) (X=A..e

    These bits can be read and written by software and can be accessed in Word Bits 15:0 mode only. Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the GPIOx_BSRR register (x = A .. E). 83/519 www.BDTIC.com/ST...

  • Page 84: Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A..e

    Note: If both BSx and BRx are set, BSx has priority. BSx: Set bit x (x= 0 .. 15) These bits are write-only and can be accessed in Word mode only. Bits 15:0 0: No action on the corresponding ODRx bit 1: Set the corresponding ODRx bit 84/519 www.BDTIC.com/ST...

  • Page 85: Port Bit Reset Register (Gpiox_Brr) (X=A..e

    These bits are write-only and can be accessed in Word mode only. Bits 15:0 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority. 85/519 www.BDTIC.com/ST...

  • Page 86: Port Configuration Lock Register (Gpiox_Lckr) (X=A..e

    Any error in the lock sequence will abort the lock. LCKx: Lock bit x (x= 0 .. 15) These bits are read write but can only be written when the LCKK bit is 0. Bits 15:0 0: Port configuration not locked 1: Port configuration locked. 86/519 www.BDTIC.com/ST...

  • Page 87: Alternate Function I/O And Debug Configuration (Afio)

    TRACED2 TRACED3 To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR). Refer to Table 15 87/519 www.BDTIC.com/ST...

  • Page 88: Timer Alternate Function Remapping

    Table 17. Timer 3 alternate function remapping TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = Alternate Function “00” (no remap) “10” (partial remap) “11” (full remap) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 1. Remap available only for 64 and 100 pin packages. 88/519 www.BDTIC.com/ST...

  • Page 89: Usart Alternate Function Remapping

    = “11” (full remap) USART3_TX PB10 PC10 USART3_RX PB11 PC11 USART3_CK PB12 PC12 PD10 USART3_CTS PB13 PD11 USART3_RTS PB14 PD12 1. Remap available only for 64 and 100 pin packages 2. Remap available only for 100 pin package. 89/519 www.BDTIC.com/ST...

  • Page 90: I2C 1 Alternate Function Remapping

    1. Remap not available on 128K 36 pin. 5.3.7 SPI 1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 24. SPI1 Remapping Alternate Function SPI1_REMAP = 0 SPI1_REMAP = 1 SPI1_NSS PA15 SPI1_SCK SPI1_MISO SPI1_MOSI 90/519 www.BDTIC.com/ST...

  • Page 91: Afio Register Description

    PIN[3:0] Pin selection (x = A .. E) Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal. 0000: Px0 selected Bits 3:0 0001: Px1 selected 0010: Px2 selected 0011: Px3 selected 1111: Px15 selected 91/519 www.BDTIC.com/ST...

  • Page 92: Af Remap And Debug I/O Configuration Register (Afio_Mapr)

    This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 on 100-pin packages only. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, Bit 12 TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped. 92/519 www.BDTIC.com/ST...
  • Page 93 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) USART1_REMAP USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX Bit 2 and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) 93/519 www.BDTIC.com/ST...
  • Page 94 This bit is set and cleared by software. It controls the mapping of SPI1 NSS, Bit 0 SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB3, MOSI/PB5) 94/519 www.BDTIC.com/ST...

  • Page 95: External Interrupt Configuration Register 1 (Afio_Exticr1)

    EXTIx[3:0]: EXTI x configuration (x= 4 to 7) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin Bits 15:0 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 95/519 www.BDTIC.com/ST...

  • Page 96: External Interrupt Configuration Register 3 (Afio_Exticr3)

    EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin Bits 15:0 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 96/519 www.BDTIC.com/ST...

  • Page 97: Gpio And Afio Register Maps

    Reset Value AFIO_MAPR Reserved Reserved Reset Value AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Reserved Reset Value AFIO_EXTICR2 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] Reserved Reset Value AFIO_EXTICR3 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Reserved Reset Value AFIO_EXTICR4 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] Reserved Reset Value 97/519 www.BDTIC.com/ST...

  • Page 98: Interrupts And Events

    0x0000_0014 settable UsageFault Undefined instruction or illegal state 0x0000_0018 0x0000_001C - Reserved 0x0000_002B System service call via SWI settable SVCall 0x0000_002C instruction settable Debug Monitor Debug Monitor 0x0000_0030 Reserved 0x0000_0034 settable PendSV Pendable request for system service 0x0000_0038 98/519 www.BDTIC.com/ST...
  • Page 99 TIM1_BRK TIM1 Break interrupt 0x0000_00A0 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4 TIM1 Trigger and Commutation settable TIM1_TRG_COM 0x0000_00A8 interrupts settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC settable TIM2 TIM2 global interrupt 0x0000_00B0 settable TIM3 TIM3 global interrupt 0x0000_00B4 99/519 www.BDTIC.com/ST...
  • Page 100 USART2 USART2 global interrupt 0x0000_00D8 settable USART3 USART3 global interrupt 0x0000_00DC settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0 settable RTCAlarm RTC alarm through EXTI line interrupt 0x0000_00E4 USB wakeup from suspend through settable USBWakeUp 0x0000_00E8 EXTI line interrupt 100/519 www.BDTIC.com/ST...

  • Page 101: External Interrupt/Event Controller (Exti)

    AMBA APB BUS PCLK2 PERIPHERAL INTERFACE RISING FALLING SOFTWARE INTERRUPT PENDING TRIGGER TRIGGER INTERRUPT MASK REQUEST SELECTION SELECTION EVENT REGISTER REGISTER REGISTER REGISTER REGISTER To NVIC Interrupt Controller EDGE DETECT PULSE Input CIRCUIT GENERATOR Line EVENT MASK REGISTER 101/519 www.BDTIC.com/ST...

  • Page 102: Wake-Up Event Management

    The 19 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt. Configure the mask bits of the 19 Interrupt/Event lines (EXTI_IMR, EXTI_EMR) Set the required bit of the software interrupt register (EXTI_SWIER) 102/519 www.BDTIC.com/ST...

  • Page 103: External Interrupt/Event Line Mapping

    EXTI line 17 is connected to the RTC Alarm event EXTI line 18 is connected to the USB Wake-up event register description EXTI Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 103/519 www.BDTIC.com/ST...
  • Page 104 MR12 MR11 MR10 Bits 31:19 Reserved, must be kept at reset value (0). MRx: Event Mask on line x Bits 18:0 0: Event request from Line x is masked 1: Event request from Line x is not masked 104/519 www.BDTIC.com/ST...
  • Page 105 If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. 105/519 www.BDTIC.com/ST...
  • Page 106 Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt Bits 18:0 request is generated. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit). 106/519 www.BDTIC.com/ST...

  • Page 107: Exti Register Map

    Reset Value EXTI_EMR MR[18:0] Reserved Reset Value EXTI_RTSR TR[18:0] Reserved Reset Value EXTI_FTSR TR[18:0] Reserved Reset Value EXTI_SWIER SWIER[18:0] Reserved Reset Value EXTI_PR PR[18:0] Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 107/519 www.BDTIC.com/ST...

  • Page 108: Dma Controller (Dma)

    Memory-to-memory transfer Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers Access to Flash, SRAM, peripheral SRAM, APB1 and APB2 peripherals as source and destination Programmable number of data to be transferred: up to 65536 The block diagram is shown in Figure 108/519 www.BDTIC.com/ST...

  • Page 109: Functional Description

    A store of the data loaded to the peripheral data register or a location in memory addressed through the DMA_CMARx register A post-decrement of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed. 109/519 www.BDTIC.com/ST...

  • Page 110: Arbiter

    If the channel is configured in non-circular mode, no DMA requests are served after the end of the transfer (i.e. once the number of data to be transferred reaches zero). Channel configuration procedure The following sequence should be followed to configure a DMA channel (where x is the channel number). 110/519 www.BDTIC.com/ST...

  • Page 111: Error Management

    EN bit in the corresponding Channel Configuration Register (DMA_CCRx). The channel's Transfer Error Interrupt Flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the Transfer Error Interrupt Enable bit (TEIE) in the DMA_CCRx register is set. 111/519 www.BDTIC.com/ST...

  • Page 112: Dma Request Mapping

    USART2_RX HW REQUEST 6 TIM1_CH3 CHANNEL 6 TIM3_CH1 TIM3_TRIG SW TRIGGER (MEM2MEM bit) I2C1_TX Channel 6 EN bit USART2_TX HW REQUEST 7 CHANNEL 7 TIM2_CH2 LOW PRIORITY TIM2_CH4 SW TRIGGER (MEM2MEM bit) TIM4_UP I2C1_RX Channel 7 EN bit 112/519 www.BDTIC.com/ST...

  • Page 113: Dma Registers

    This bit is set by hardware. It is cleared by software writing 1 to the Bits 27, 23, 19, corresponding bit in the DMA_IFCR register. 15, 11, 7, 3 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x 113/519 www.BDTIC.com/ST...
  • Page 114 This bit is set by hardware. It is cleared by software writing 1 to the Bits 24, 20, 16, corresponding bit in the DMA_IFCR register. 12, 8, 4, 0 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x 114/519 www.BDTIC.com/ST...

  • Page 115: Dma Interrupt Flag Clear Register (Dma

    CGIFx: Channel x Global interrupt clear (x = 1 ..7) Bits 24, 20, 16, This bit is set and cleared by software. 12, 8, 4, 0 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register 115/519 www.BDTIC.com/ST...

  • Page 116: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1

    This bit is set and cleared by software. Bit 7 0: Memory increment mode disabled 1: Memory increment mode enabled PINC: Peripheral increment mode This bit is set and cleared by software. Bit 6 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled 116/519 www.BDTIC.com/ST...

  • Page 117: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1

    Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 117/519 www.BDTIC.com/ST...

  • Page 118: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1

    [1:0] [1:0] Reset Value DMA_CNDTR1 NDT[15:0] 00Ch Reserved Reset Value DMA_CPAR1 PA[31:0] 010h Reset Value DMA_CMAR1 MA[31:0] 014h Reset Value 018h Reserved PSIZE DMA_CCR2 SIZE [1:0] [1:0] 01Ch Reserved [1:0] Reset Value DMA_CNDTR2 NDT[15:0] 020h Reserved Reset Value 118/519 www.BDTIC.com/ST...
  • Page 119 04Ch Reset Value DMA_CMAR4 MA[31:0] 050h Reset Value 054h Reserved PSIZE DMA_CCR5 SIZE [1:0] [1:0] 058h Reserved [1:0] Reset Value DMA_CNDTR5 NDT[15:0] 05Ch Reserved Reset Value DMA_CPAR5 PA[31:0] 060h Reset Value DMA_CMAR5 MA[31:0] 064h Reset Value 068h Reserved 119/519 www.BDTIC.com/ST...
  • Page 120 SIZE [1:0] [1:0] 080h Reserved [1:0] Reset Value DMA_CNDTR7 NDT[15:0] 084h Reserved Reset Value DMA_CPAR7 PA[31:0] 088h Reset Value DMA_CMAR7 MA[31:0] 08Ch Reset Value 090h Reserved Refer to Table 1 on page 27 for the register boundary addresses. 120/519 www.BDTIC.com/ST...

  • Page 121: Real-Time Clock (Rtc)

    32-bit programmable counter that can be initialized to the current system time. The system time is incremented at the TR_CLK rate and compared with a programmable date (stored in the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR control register. 121/519 www.BDTIC.com/ST...

  • Page 122: Figure 18. Rtc Simplified Block Diagram

    RTC_CNT rising OWIE edge RTC_Alarm RTC prescaler ALRF ALRIE RTC_ALR not powered in STANDBY powered in STANDBY NVIC INTERRUPT CONTROLLER powered in STANDBY not powered in STANDBY RTC_Alarm EXIT FROM WKUP pin STANDBY MODE WKP_STDBY powered in STANDBY 122/519 www.BDTIC.com/ST...

  • Page 123: Resetting Rtc Registers

    Consequently when reading the RTC registers, after having disabled the RTC APB1 interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the RTC_CRL register to be set by hardware. Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes. 123/519 www.BDTIC.com/ST...

  • Page 124: Configuring Rtc Registers

    0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT 0000 0001 0002 0003 0004 0005 RTC_ALARM 1 RTCCLK ALRF can be cleared by software (not powered in STANDBY) 124/519 www.BDTIC.com/ST...

  • Page 125: Rtc Register Description

    It is not possible to write to the RTC_CRH register when the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 8.3.4 on page 124). The RTC functions are controlled by this control register. Some bits must be written using a specific configuration procedure (see Configuration procedure:). 125/519 www.BDTIC.com/ST...

  • Page 126: Rtc Control Register Low (Rtc_Crl)

    RTC counter (usually Bit 0 one second). An interrupt is generated if SECIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Second flag condition not met. 1: Second flag condition met. 126/519 www.BDTIC.com/ST...
  • Page 127 If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI Controller in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is generated on this line (no RTC Alarm interrupt generation). 127/519 www.BDTIC.com/ST...

  • Page 128: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)

    These bits are used to define the counter clock frequency according to the following Bits 15:0 formula: /(PRL[19:0]+1) TR_CLK RTCCLK Note: If the input clock frequency (f ) is 32.768 kHz, write 7FFFh in this register to get a RTCCLK signal period of 1 second. 128/519 www.BDTIC.com/ST...

  • Page 129: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)

    Address Offset: 10h Reset value: 0000h Reserved RTC_DIV[19:16] Bits 15:4 Reserved Bits 3:0 RTC_DIV[19:16]: RTC Clock Divider High RTC prescaler divider register low (RTC_DIVL) Address Offset: 14h Reset value: 8000h RTC_DIV[15:0] Bits 15:0 RTC_DIV[15:0]: RTC Clock Divider Low 129/519 www.BDTIC.com/ST...

  • Page 130: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)

    Reading the RTC_CNTL register, the current value of the lower part of the RTC Bits 15:0 Counter register is returned. To write to this register it is necessary to enter configuration mode using the RTOFF bit in the RTC_CR register. 130/519 www.BDTIC.com/ST...

  • Page 131: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)

    RTC_ALR[15:0]: RTC Alarm Low The low part of the alarm time is written by software in this register. To write to this Bits 15:0 register it is necessary to enter configuration mode using the RTOFF bit in the RTC_CR register. 131/519 www.BDTIC.com/ST...

  • Page 132: Rtc Register Map

    Reset Value 018h RTC_CNTH CNT[13:16] Reserved Reset Value RTC_CNTL CNT[15:0] 01Ch Reserved Reset Value RTC_ALRH ALR[31:16] 020h Reserved Reset Value RTC_ALRL ALR[15:0] 024h Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 132/519 www.BDTIC.com/ST...

  • Page 133: Backup Registers (Bkp)

    Tamper pin value still indicates a Tamper detection. This is equivalent to a level detection on the Tamper pin. Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting of the data backup registers, the ANTI_TAMP pin should be externally tied to the correct level. 133/519 www.BDTIC.com/ST...

  • Page 134: Rtc Calibration

    This value indicates the number of clock pulses that will be ignored every 2^20 clock Bit 6:0 pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM. The clock of the RTC can be slowed down from 0 to 121PPM. 134/519 www.BDTIC.com/ST...

  • Page 135: Backup Control Register (Bkp_Cr)

    Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the value will not be stored. Bits 7:3 Reserved, always read as 0. 135/519 www.BDTIC.com/ST...
  • Page 136 1: Clear the Tamper interrupt and the TIF Tamper interrupt flag. CTE Clear Tamper event This bit is write only, and is always read as 0. Bit 0 0: No effect 1: Reset the TEF Tamper event flag (and the Tamper detector) 136/519 www.BDTIC.com/ST...

  • Page 137: Bkp Register Map

    Reset Value BKP_DR9 D[15:0] Reserved Reset Value D[15:0] BKP_DR10 Reserved Reset Value BKP_RTCCR CAL[6:0] Reserved Reset Value BKP_CR Reserved Reset Value BKP_CSR Reserved Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 137/519 www.BDTIC.com/ST...

  • Page 138: Independent Watchdog (Iwdg)

    When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and watchdog and bxCAN. 138/519 www.BDTIC.com/ST...

  • Page 139: Iwdg Register Description

    RC period of uncertainty. 10.2 IWDG register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 10.2.1 Key register (IWDG_KR) Address Offset: 00h Reset value: 00000000h (reset by STANDBY mode) Reserved KEY[15:0] 139/519 www.BDTIC.com/ST...
  • Page 140 AAAAh, otherwise the watchdog generates a reset when the counter reaches Bits 15:0 Writing the key value 5555h to enables access to the IWDG_PR and IWDG_RLR registers (see Section 10.1.2) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 140/519 www.BDTIC.com/ST...

  • Page 141: Prescaler Register (Iwdg_Pr)

    This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. 141/519 www.BDTIC.com/ST...

  • Page 142: Reload Register (Iwdg_Rlr)

    For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 10.2.4 Status register (IWDG_SR) Address Offset: 0Ch Reset value: 00000000h (not reset by STANDBY mode) Reserved Reserved 142/519 www.BDTIC.com/ST...
  • Page 143 However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete) 143/519 www.BDTIC.com/ST...

  • Page 144: Iwdg Register Map

    IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] Reserved Reset Value IWDG_PR PR[2:0] Reserved Reset Value IWDG_RLR RL[11:0] Reserved Reset Value IWDG_SR Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 144/519 www.BDTIC.com/ST...

  • Page 145: Window Watchdog (Wwdg)

    6-BIT DOWNCOUNTER (CNT) PCLK1 (from RCC clock controller) WDG PRESCALER (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter 145/519 www.BDTIC.com/ST...

  • Page 146: How To Program The Watchdog Timeout

    If more precision is needed, use the formulae in Figure Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. 146/519 www.BDTIC.com/ST...

  • Page 147: Debug Mode

    When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and watchdog and bxCAN. 147/519 www.BDTIC.com/ST...

  • Page 148: Register Description

    Reset Value: 0111 1111 (7Fh) Reserved Reserved Bit 31:10 Reserved EWI: Early Wakeup Interrupt Bit 9 When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is only cleared by hardware after a reset. 148/519 www.BDTIC.com/ST...

  • Page 149: Status Register (Wwdg_Sr)

    This bit is set by hardware when the counter has reached the value 40h. It Bit 0 must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not enabled. 149/519 www.BDTIC.com/ST...

  • Page 150: Wwdg Register Map

    WWDG register map Table 35. WWDG register map and reset values Offset Register WWDG_CR T[6:0] Reserved Reset Value WWDG_CFR W[6:0] Reserved Reset Value WWDG_SR Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 150/519 www.BDTIC.com/ST...

  • Page 151: Advanced Control Timer (Tim1)

    Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger – Input capture – Output compare – Break input 151/519 www.BDTIC.com/ST...

  • Page 152: Block Diagram

    Capture/Compare 4 Register TIM1_CH4 EdgeDetector control ETRF Polarity Selection TIM1_BKIN Clock failure event from clock controller CSS (Clock Security system Notes: Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output 152/519 www.BDTIC.com/ST...

  • Page 153: Functional Description

    It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 25 Figure 26 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 153/519 www.BDTIC.com/ST...

  • Page 154: Counter Modes

    Setting the UG bit in the TIM1_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIM1_CR1 register. This is to avoid updating the shadow registers while writing new values in the 154/519 www.BDTIC.com/ST...

  • Page 155: Figure 27. Counter Timing Diagram, Internal Clock Divided By 1

    UPDATE INTERRUPT FLAG (UIF) Figure 28. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 0034 0035 0036 0000 0001 0002 0003 COUNTER OVERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) 155/519 www.BDTIC.com/ST...

  • Page 156: Figure 29. Counter Timing Diagram, Internal Clock Divided By 4

    CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 COUNTER OVERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) AUTO-RELOAD REGISTER Write a new value in TIM1_ARR 156/519 www.BDTIC.com/ST...

  • Page 157: Figure 32. Counter Timing Diagram, Update Event When Arpe=1 (Tim1_Arr Preloaded)

    TIM1_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. The following figures show some examples of the counter behavior for different clock frequencies when TIM1_ARR=0x36. 157/519 www.BDTIC.com/ST...

  • Page 158: Figure 33. Counter Timing Diagram, Internal Clock Divided By 1

    UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) Figure 35. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 0001 0000 0036 0035 COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) 158/519 www.BDTIC.com/ST...

  • Page 159: Figure 37. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used

    This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. 159/519 www.BDTIC.com/ST...

  • Page 160: Figure 38. Counter Timing Diagram, Internal Clock Divided By 1, Tim1_Arr=0X6

    Note: Here, center-aligned mode 1 is used Figure 39. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 0003 0002 0001 0000 0001 0002 0003 COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) 160/519 www.BDTIC.com/ST...

  • Page 161: Figure 40. Counter Timing Diagram, Internal Clock Divided By 4, Tim1_Arr=0X36

    TIMER CLOCK = CK_CNT COUNTER REGISTER 05 04 03 02 01 01 02 03 04 05 06 07 COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) AUTO-RELOAD PRELOAD REGISTER Write a new value in TIM1_ARR AUTO-RELOAD ACTIVE REGISTER 161/519 www.BDTIC.com/ST...

  • Page 162: Repetition Down-Counter

    (by setting the UG bit in TIM1_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition down- counter is and the repetition down-counter is reloaded with the content of the TIM1_RCR register. 162/519 www.BDTIC.com/ST...

  • Page 163: Figure 44. Update Rate Examples Depending On Mode And Tim1_Rcr Register Settings

    (by SW) (by SW) (by SW) UEV Update Event: Preload registers transferred to active registers and update interrupt generated Update Event if the repetition down-counter underflow occurs when the counter is equal to to the auto-reload value. 163/519 www.BDTIC.com/ST...

  • Page 164: Clock Selection

    TS[2:0] ti2f ti1f encoder ITR1 mode ti1f_ed external clock trgi ti1fp1 mode 1 ck_psc ti2f_rising ti2fp2 Edge Filter Detector ti2f_falling etrf external clock etrf mode 2 ICF[3:0] CC2P CK_INT internal clock mode TIM1_CCMR1 TIM1_CCER (internal clock) SMS[2:0] TIM1_SMCR 164/519 www.BDTIC.com/ST...

  • Page 165: Figure 47. Control Circuit In External Clock Mode 1

    1 ck_psc ETR pin ETRP ETRF external clock divider filter mode 2 down-counter /1, /2, /4, /8 CK_INT internal clock mode (internal clock) ETPS[1:0] ETF[3:0] TIM1_SMCR TIM1_SMCR TIM1_SMCR SMS[2:0] TIM1_SMCR 165/519 www.BDTIC.com/ST...

  • Page 166: Capture/Compare Channels

    The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 166/519 www.BDTIC.com/ST...

  • Page 167: Figure 50. Capture/Compare Channel (Example: Channel 1 Input Stage)

    CCR1H read_in_progress write CCR1L Capture/Compare Preload Register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/Compare Shadow Register CC1S[0] TIM1_CCMR1 (from time comparator ic1ps capture base unit) CC1E CNT>CCR1 Counter CNT=CCR1 CC1G TIM1_EGR 167/519 www.BDTIC.com/ST...

  • Page 168: Input Capture Mode

    ‘0’ or by reading the captured data stored in the TIM1_CCRx register (when you read the low byte in case of 16-bit register). CCxOF is cleared when you write it to ‘0’. 168/519 www.BDTIC.com/ST...

  • Page 169: Pwm Input Mode

    Two ICx signals are mapped on the same TIx input. These 2 ICx signals are active on edges with opposite polarity. One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. 169/519 www.BDTIC.com/ST...

  • Page 170: Forced Output Mode

    Anyway, the comparison between the TIM1_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section below. 170/519 www.BDTIC.com/ST...

  • Page 171: Output Compare Mode

    The TIM1_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIM1_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 171/519 www.BDTIC.com/ST...

  • Page 172: Pwm Mode

    In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIM1_CNT <TIM1_CCRx else it becomes low. If the compare value in TIM1_CCRx is greater than the auto-reload value (in TIM1_ARR) then OCxREF is held at 172/519 www.BDTIC.com/ST...

  • Page 173: Figure 56. Edge-Aligned Pwm Waveforms (Arr=8)

    PWM waveforms in an example where: TIM1_ARR=8, PWM mode is the PWM mode 1, The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIM1_CR1 register. 173/519 www.BDTIC.com/ST...

  • Page 174: Complementary Outputs And Dead-Time Insertion

    OISxN, OSSI and OSSR bits in the TIM1_BDTR and TIM1_CR2 registers. Refer to Table 37: Output control bits for complementary OCx and OCxN channels with break feature on page 211 for more details. In particular, the dead-time is activated when switching to the IDLE state (MOE falling down to 0). 174/519 www.BDTIC.com/ST...

  • Page 175: Figure 58. Complementary Output With Dead-Time Insertion

    The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIM1_BDTR register. Refer to Section 12.5.18: Break and dead-time register (TIM1_BDTR) on page 216 for delay calculation. 175/519 www.BDTIC.com/ST...

  • Page 176: Using The Break Function

    This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits 176/519 www.BDTIC.com/ST...
  • Page 177 LOCK bits in the TIM1_BDTR register. Refer to Section 12.5.18: Break and dead-time register (TIM1_BDTR) on page 216. The LOCK bits can be written only once after an MCU reset. Figure 61 shows an example of behavior of the outputs in response to a break. 177/519 www.BDTIC.com/ST...

  • Page 178: Figure 61. Output Behavior In Response To A Break

    (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1) delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1) delay OCxN (CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0) OCxN (CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1) 178/519 www.BDTIC.com/ST...

  • Page 179: Clearing The Ocxref Signal On An External Event

    OCxCE. In this example, the timer TIM1 is programmed in PWM mode. Figure 62. Clearing TIM1 OCxREF (CCRx) counter (CNT) ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) OCREF_CLR OCREF_CLR becomes high still high 179/519 www.BDTIC.com/ST...

  • Page 180: 6-Step Pwm Generation

    CCxNE=0 OCxM=110 (PWM1) OCxM=100 EXAMPLE 1 OCxN CCxE=1 Write CCxNE to 1 CCxE=0 CCxNE=0 CCxNE=1 OCxM=100 (forced active) OCxM=101 EXAMPLE 2 OCxN CCxE=1 Write CCxE and CxNE to 0 CCxE=1 CCxNE=1 CCxNE=0 OCxM=110 (PWM1) OCxM=100 EXAMPLE 3 OCxN 180/519 www.BDTIC.com/ST...

  • Page 181: One Pulse Mode

    TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIM1_CCER register. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIM1_SMCR register. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIM1_SMCR register (trigger mode). 181/519 www.BDTIC.com/ST...

  • Page 182: Encoder Interface Mode

    0 and the auto-reload value in the TIM1_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIM1_ARR before starting. in the same way, the capture, compare, prescaler, 182/519 www.BDTIC.com/ST...

  • Page 183: Table 36. Counting Direction Versus Encoder Signals

    CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2). CC1P=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1). CC2P=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2). SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges). CEN=’1’ (TIMx_CR1 register, Counter enabled). 183/519 www.BDTIC.com/ST...

  • Page 184: Figure 65. Example Of Counter Operation In Encoder Interface Mode

    You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. 184/519 www.BDTIC.com/ST...

  • Page 185: Timer Input Xor Function

    (CCUS=1 in the TIM1_CR2 register). The PWM control bits (CCxE, OCxM) are written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). 185/519 www.BDTIC.com/ST...

  • Page 186: Figure 67. Example Of Hall Sensor Interface

    UM0306 Figure 67 describes this example. Figure 67. Example of Hall sensor interface TIH1 TIH2 TIH3 counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step 186/519 www.BDTIC.com/ST...

  • Page 187: Timers And External Trigger Synchronization

    The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 68. Control circuit in reset mode COUNTER CLOCK = ck_cnt = ck_psc COUNTER REGISTER 32 33 34 35 36 01 02 03 00 01 02 03 187/519 www.BDTIC.com/ST...

  • Page 188: Figure 69. Control Circuit In Gated Mode

    The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 69. Control circuit in gated mode cnt_en COUNTER CLOCK = ck_cnt = ck_psc COUNTER REGISTER 32 33 35 36 37 38 Write TIF=0 188/519 www.BDTIC.com/ST...

  • Page 189: Figure 70. Control Circuit In Trigger Mode

    It is recommended not to select ETR as TRGI through the TS bits of TIM1_SMCR register. In the following example, the up-counter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 189/519 www.BDTIC.com/ST...

  • Page 190: Timer Synchronization

    When the microcontroller enters debug mode (Cortex-M3 core halted), the TIM1 counter either continues to work normally or stops, depending on DBG_TIM1_STOP configuration bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and watchdog and bxCAN. 190/519 www.BDTIC.com/ST...

  • Page 191: Tim1 Register Description

    Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. OPM: One pulse mode. Bit 3 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN). 191/519 www.BDTIC.com/ST...
  • Page 192 0: Counter disabled 1: Counter enabled Bit 0 Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 192/519 www.BDTIC.com/ST...

  • Page 193: Control Register 2 (Tim1_Cr2)

    Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM1_BKR register). TI1S: TI1 Selection. 0: The TIM1_CH1 pin is connected to TI1 input. Bit 7 1: The TIM1_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) 193/519 www.BDTIC.com/ST...
  • Page 194 0: CCxE, CCxNE and OCxM bits are not preloaded Bit 0 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output. 194/519 www.BDTIC.com/ST...

  • Page 195: Slave Mode Control Register (Tim1_Smcr)

    A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. Bits 13:12 00: Prescaler OFF. 01: ETRP frequency divided by 2. 10: ETRP frequency divided by 4. 11: ETRP frequency divided by 8. 195/519 www.BDTIC.com/ST...
  • Page 196 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 196/519 www.BDTIC.com/ST...
  • Page 197 Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. 197/519 www.BDTIC.com/ST...

  • Page 198: Dma/Interrupt Enable Register (Tim1_Dier)

    Bit 6 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. COMIE: COM interrupt enable. Bit 5 0: COM interrupt disabled. 1: COM interrupt enabled. CC4IE: Capture/Compare 4 interrupt enable. Bit 4 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. 198/519 www.BDTIC.com/ST...
  • Page 199 Bit 2 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. CC1IE: Capture/Compare 1 interrupt enable. Bit 1 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. UIE: Update interrupt enable. Bit 0 0: Update interrupt disabled. 1: Update interrupt enabled. 199/519 www.BDTIC.com/ST...

  • Page 200: Status Register (Tim1_Sr)

    0: No COM event occurred. 1: COM interrupt pending. CC4IF: Capture/Compare 4 interrupt Flag. Bit 4 refer to CC1IF description CC3IF: Capture/Compare 3 interrupt Flag. Bit 3 refer to CC1IF description CC2IF: Capture/Compare 2 interrupt Flag. Bit 2 refer to CC1IF description 200/519 www.BDTIC.com/ST...
  • Page 201 – When CNT is reinitialized by software using the UG bit in TIM1_EGR register, if URS=0 and UDIS=0 in the TIM1_CR1 register. – When CNT is reinitialized by a trigger event (refer to Section 12.5.3: Slave mode control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIM1_CR1 register. 201/519 www.BDTIC.com/ST...

  • Page 202: Event Generation Register (Tim1_Egr)

    Note: This bit acts only on channels having a complementary output. CC4G: Capture/Compare 4 Generation. Bit 4 refer to CC1G description CC3G: Capture/Compare 3 Generation. Bit 3 refer to CC1G description CC2G: Capture/Compare 2 Generation. Bit 2 refer to CC1G description 202/519 www.BDTIC.com/ST...
  • Page 203 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (up-counting), else it takes the auto-reload value (TIM1_ARR) if DIR=1 (down-counting). 203/519 www.BDTIC.com/ST...

  • Page 204: Capture/Compare Mode Register 1 (Tim1_Ccmr1)

    TIM1_CCER). OC1CE: Output Compare 1Clear Enable OC1CE: Output Compare 1 Clear Enable Bit 7 0: OC1Ref is not affected by the ETRF Input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 204/519 www.BDTIC.com/ST...
  • Page 205 (LOCK bits in TIM1_BDTR register) and CC1S=’00’ (the channel is configured in output). Note 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIM1_CR1 register). Else the behavior is not guaranteed. 205/519 www.BDTIC.com/ST...
  • Page 206 11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is working only if an internal trigger input is selected through TS bit (TIM1_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in TIM1_CCER). 206/519 www.BDTIC.com/ST...
  • Page 207 11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is working only if an internal trigger input is selected through TS bit (TIM1_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in TIM1_CCER). 207/519 www.BDTIC.com/ST...

  • Page 208: Capture/Compare Mode Register 2 (Tim1_Ccmr2)

    TS bit (TIM1_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in TIM1_CCER). Input capture mode Bits 15:12 IC4F: Input Capture 4 Filter. Bits 11:10 IC4PSC: Input Capture 4 Prescaler. 208/519 www.BDTIC.com/ST...

  • Page 209: Capture/Compare Enable Register (Tim1_Ccer)

    CC1NP description CC3NE: Capture/Compare 3 Complementary output enable. Bit 10 refer to CC1NE description CC3P: Capture/Compare 3 output Polarity. Bit 9 refer to CC1P description CC3E: Capture/Compare 3 output enable. Bit 8 refer to CC1E description 209/519 www.BDTIC.com/ST...
  • Page 210 OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIM1_CCR1) or not. 0: Capture disabled. 1: Capture enabled. 210/519 www.BDTIC.com/ST...

  • Page 211: Table 37. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature

    OISx and OISxN don’t correspond to OCX and OCxN both to active state Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers. 211/519 www.BDTIC.com/ST...

  • Page 212: Counter (Tim1_Cnt)

    ARR is the value to be loaded in the actual auto-reload register. Bits 15:0 Refer to the Section 12.4.1: Time base unit on page 153 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 212/519 www.BDTIC.com/ST...

  • Page 213: Repetition Counter Register (Tim1_Rcr)

    The active capture/compare register contains the value to be compared to the counter TIM1_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 213/519 www.BDTIC.com/ST...

  • Page 214: Capture/Compare Register 2 (Tim1_Ccr2)

    The active capture/compare register contains the value to be compared to the counter TIM1_CNT and signalled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 214/519 www.BDTIC.com/ST...

  • Page 215: Capture/Compare Register 4 (Tim1_Ccr4)

    The active capture/compare register contains the value to be compared to the counter TIM1_CNT and signalled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). 215/519 www.BDTIC.com/ST...

  • Page 216: Break And Dead-Time Register (Tim1_Bdtr)

    1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1 Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIM1_BDTR register). 216/519 www.BDTIC.com/ST...
  • Page 217 (LOCK bits in TIM1_BDTR register). Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIM1_BDTR register. 217/519 www.BDTIC.com/ST...

  • Page 218: Dma Control Register (Tim1_Dcr)

    TIM1_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM1_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIM1_DCR register. 218/519 www.BDTIC.com/ST...

  • Page 219: Tim1 Register Map

    Input Capture [1:0] [1:0] Reserved mode [1:0] [1:0] Reset Value TIM1_CCER Reserved Reset Value TIM1_CNT CNT[15:0] Reserved Reset Value TIM1_PSC PSC[15:0] Reserved Reset Value TIM1_ARR ARR[15:0] Reserved Reset Value TIM1_RCR REP[7:0] Reserved Reset Value TIM1_CCR1 CCR1[15:0] Reserved Reset Value 219/519 www.BDTIC.com/ST...
  • Page 220 Reset Value TIM1_CCR4 CCR4[15:0] Reserved Reset Value LOCK TIM1_BDTR DT[7:0] [1:0] Reserved Reset Value TIM1_DCR DBL[4:0] DBA[4:0] Reserved Reserved Reset Value TIM1_DMAR DMAB[15:0] Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 220/519 www.BDTIC.com/ST...

  • Page 221: General Purpose Timer (Timx)

    Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger – Input capture – Output compare 221/519 www.BDTIC.com/ST...

  • Page 222: Block Diagram

    The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. 222/519 www.BDTIC.com/ST...

  • Page 223: Figure 73. Counter Timing Diagram With Prescaler Division Change From 1 To 2

    Figure 73. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER F9 FA FB FC UPDATE EVENT (UEV) PRESCALER CONTROL REGISTER Write a new value in TIMx_PSC PRESCALER BUFFER PRESCALER COUNTER 223/519 www.BDTIC.com/ST...

  • Page 224: Counter Modes

    The auto-reload shadow register is updated with the preload value (TIMx_ARR), The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. 224/519 www.BDTIC.com/ST...

  • Page 225: Figure 75. Counter Timing Diagram, Internal Clock Divided By 1

    UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) Figure 77. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 0035 0036 0000 0001 COUNTER OVERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) 225/519 www.BDTIC.com/ST...

  • Page 226: Figure 78. Counter Timing Diagram, Internal Clock Divided By N

    CK_INT CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 COUNTER OVERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) AUTO-RELOAD REGISTER Write a new value in TIMx_ARR 226/519 www.BDTIC.com/ST...

  • Page 227: Figure 80. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)

    The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. 227/519 www.BDTIC.com/ST...

  • Page 228: Figure 81. Counter Timing Diagram, Internal Clock Divided By 1

    UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) Figure 83. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 0001 0000 0036 0035 COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) 228/519 www.BDTIC.com/ST...

  • Page 229: Figure 84. Counter Timing Diagram, Internal Clock Divided By N

    This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. 229/519 www.BDTIC.com/ST...

  • Page 230: Figure 86. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6

    Note: Here, center-aligned mode 1 is used Figure 87. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 0003 0002 0001 0000 0001 0002 0003 COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) 230/519 www.BDTIC.com/ST...

  • Page 231: Figure 88. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36

    TIMER CLOCK = CK_CNT COUNTER REGISTER 05 04 03 02 01 01 02 03 04 05 06 07 COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF) AUTO-RELOAD PRELOAD REGISTER Write a new value in TIMx_ARR AUTO-RELOAD ACTIVE REGISTER 231/519 www.BDTIC.com/ST...

  • Page 232: Clock Selection

    (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 92 shows the behavior of the control circuit and the up-counter in normal mode, without prescaler. 232/519 www.BDTIC.com/ST...

  • Page 233: Figure 92. Control Circuit In Normal Mode, Internal Clock Divided By 1

    Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. Enable the counter by writing CEN=1 in the TIMx_CR1 register. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. 233/519 www.BDTIC.com/ST...

  • Page 234: Figure 94. Control Circuit In External Clock Mode 1

    Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. 234/519 www.BDTIC.com/ST...

  • Page 235: Capture/Compare Channels

    TI2F_rising (from channel 2) CC1S[1:0] ICPS[1:0] CC1E TI2F_falling TIMx_CCMR1 TIMx_CCER (from channel 2) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. 235/519 www.BDTIC.com/ST...

  • Page 236: Input Capture Mode

    CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be 236/519 www.BDTIC.com/ST...

  • Page 237: Pwm Input Mode

    Two ICx signals are mapped on the same TIx input. These 2 ICx signals are active on edges with opposite polarity. One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. 237/519 www.BDTIC.com/ST...

  • Page 238: Forced Output Mode

    Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 238/519 www.BDTIC.com/ST...

  • Page 239: Output Compare Mode

    The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 101. 239/519 www.BDTIC.com/ST...

  • Page 240: Pwm Mode

    “frozen” configuration (no comparison, OCxM=‘000’) to one of the PWM modes (OCxM=‘110’ or ‘111’). This allows to force the PWM by software while running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. 240/519 www.BDTIC.com/ST...

  • Page 241: Figure 102. Edge-Aligned Pwm Waveforms (Arr=8)

    PWM waveforms in an example where: TIMx_ARR=8, PWM mode is the PWM mode 1, The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. 241/519 www.BDTIC.com/ST...

  • Page 242: One Pulse Mode

    A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must In up-counting: CNT<CCRx≤ARR (in particular, 0<CCRx), In down-counting: CNT>CCRx. 242/519 www.BDTIC.com/ST...

  • Page 243: Figure 104. Example Of One Pulse Mode

    0). Particular case: OCx fast enable: In One Pulse Mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the 243/519 www.BDTIC.com/ST...

  • Page 244: Clearing The Ocxref Signal On An External Event

    OCxCE. In this example, the timer TIMx is programmed in PWM mode. Figure 105. Clearing TIMx OCxREF (CCRx) counter (CNT) ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) OCREF_CLR OCREF_CLR becomes high still high 244/519 www.BDTIC.com/ST...

  • Page 245: Table 39. Counting Direction Versus Encoder Signals

    Figure 106 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are 245/519 www.BDTIC.com/ST...

  • Page 246: Figure 106. Example Of Counter Operation In Encoder Interface Mode

    The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read 246/519 www.BDTIC.com/ST...
  • Page 247 XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in Section 12.4.18 on page 185. 247/519 www.BDTIC.com/ST...

  • Page 248: Figure 108. Control Circuit In Reset Mode

    The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 108. Control circuit in reset mode COUNTER CLOCK = ck_cnt = ck_psc COUNTER REGISTER 32 33 34 35 36 01 02 03 00 01 02 03 248/519 www.BDTIC.com/ST...

  • Page 249: Figure 109. Control Circuit In Gated Mode

    The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 109. Control circuit in gated mode cnt_en COUNTER CLOCK = ck_cnt = ck_psc COUNTER REGISTER 32 33 35 36 37 38 Write TIF=0 249/519 www.BDTIC.com/ST...

  • Page 250: Figure 110. Control Circuit In Trigger Mode

    The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 110. Control circuit in trigger mode cnt_en COUNTER CLOCK = ck_cnt = ck_psc COUNTER REGISTER 35 36 37 38 250/519 www.BDTIC.com/ST...

  • Page 251: Figure 111. Control Circuit In External Clock Mode 2 + Trigger Mode

    The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode. The following figure presents an overview of the trigger selection and the master mode 251/519 www.BDTIC.com/ST...

  • Page 252: Figure 112. Master/Slave Timer Example

    Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register). Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 counter enable signal. 252/519 www.BDTIC.com/ST...

  • Page 253: Figure 113. Gating Timer 2 With Oc1Ref Of Timer 1

    Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL). Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register). Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). Stop Timer 1 by writing ‘0’ in the CEN bit (TIM1_CR1 register). 253/519 www.BDTIC.com/ST...

  • Page 254: Figure 114. Gating Timer 2 With Enable Of Timer 1

    Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register). Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register). Figure 115. Triggering Timer 2 with UPDATE of Timer 1 CK_INT TIMER1-UEV TIMER1-CNT TIMER2-CNT TIMER2-CEN=cnt_en TIMER 2-TIF Write TIF=0 254/519 www.BDTIC.com/ST...

  • Page 255: Figure 116. Triggering Timer 2 With Enable Of Timer 1

    Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1. Refer to Figure 112 for connections. To ensure the 255/519 www.BDTIC.com/ST...

  • Page 256: Figure 117. Triggering Timer 1 And 2 With Timer 1 Ti1 Input

    When the microcontroller enters debug mode (Cortex-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and watchdog and bxCAN. 256/519 www.BDTIC.com/ST...
  • Page 257 Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. OPM: One Pulse Mode. Bit 3 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN). 257/519 www.BDTIC.com/ST...
  • Page 258 Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one pulse mode, when an update event occurs. 258/519 www.BDTIC.com/ST...
  • Page 259 111: Compare - OC4REF signal is used as trigger output (TRGO). CCDS: Capture/Compare DMA Selection. Bit 3 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bits 2:0 Reserved, always read as 0 259/519 www.BDTIC.com/ST...
  • Page 260 ETRP frequency. It is useful when inputting fast external clocks. Bits 13:12 00: Prescaler OFF. 01: ETRP frequency divided by 2. 10: ETRP frequency divided by 4. 11: ETRP frequency divided by 8. 260/519 www.BDTIC.com/ST...
  • Page 261 101: Filtered Timer Input 1 (TI1FP1). 110: Filtered Timer Input 2 (TI2FP2). 111: External Trigger input (ETRF). Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. 261/519 www.BDTIC.com/ST...
  • Page 262 Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. 262/519 www.BDTIC.com/ST...
  • Page 263 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. CC3IE: Capture/Compare 3 interrupt enable. Bit 3 0: CC3 interrupt disabled. 1: CC3 interrupt enabled. CC2IE: Capture/Compare 2 interrupt enable. Bit 2 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. 263/519 www.BDTIC.com/ST...
  • Page 264 General purpose timer (TIMx) UM0306 CC1IE: Capture/Compare 1 interrupt enable. Bit 1 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. UIE: Update interrupt enable. Bit 0 0: Update interrupt disabled. 1: Update interrupt enabled. 264/519 www.BDTIC.com/ST...
  • Page 265 Reserved, always read as 0. CC4IF: Capture/Compare 4 interrupt Flag. Bit 4 refer to CC1IF description CC3IF: Capture/Compare 3 interrupt Flag. Bit 3 refer to CC1IF description CC2IF: Capture/Compare 2 interrupt Flag. Bit 2 refer to CC1IF description 265/519 www.BDTIC.com/ST...
  • Page 266 – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. 266/519 www.BDTIC.com/ST...
  • Page 267 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (up-counting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (down-counting). 267/519 www.BDTIC.com/ST...
  • Page 268 TIMx_CCER). OC1CE: Output Compare 1Clear Enable OC1CE: Output Compare 1 Clear Enable Bit 7 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input 268/519 www.BDTIC.com/ST...
  • Page 269 (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). Note 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. 269/519 www.BDTIC.com/ST...
  • Page 270 11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in TIMx_CCER). 270/519 www.BDTIC.com/ST...
  • Page 271 11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in TIMx_CCER). 271/519 www.BDTIC.com/ST...
  • Page 272 TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in TIMx_CCER). Input capture mode Bits 15:12 IC4F: Input Capture 4 Filter. Bits 11:10 IC4PSC: Input Capture 4 Prescaler. 272/519 www.BDTIC.com/ST...
  • Page 273 11: CC3 channel is configured as input, IC3 is mapped on TRGI. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in TIMx_CCER). 273/519 www.BDTIC.com/ST...
  • Page 274 1: On - OC1 signal is output on the corresponding output pin. Bit 0 CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. 274/519 www.BDTIC.com/ST...

  • Page 275: Table 40. Output Control Bit For Standard Ocx Channels

    Reset value: 0000h PSC[15:0] PSC[15:0]: Prescaler Value. The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC Bits 15:0 PSC contains the value to be loaded in the active prescaler register at each update event. 275/519 www.BDTIC.com/ST...
  • Page 276 The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 276/519 www.BDTIC.com/ST...
  • Page 277 The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 277/519 www.BDTIC.com/ST...
  • Page 278 The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2/ if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 278/519 www.BDTIC.com/ST...
  • Page 279 TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in the TIMx_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register. 279/519 www.BDTIC.com/ST...

  • Page 280: Table 41. Timx - Register Map And Reset Values

    CC3S IC4F[3:0] IC3F[3:0] Input Capture [1:0] [1:0] Reserved [1:0] [1:0] mode Reset Value TIMx_CCER Reserved Reset Value TIMx_CNT CNT[15:0] Reserved Reset Value TIMx_PSC PSC[15:0] Reserved Reset Value TIMx_ARR ARR[15:0] Reserved Reset Value Reserved TIMx_CCR1 CCR1[15:0] Reserved Reset Value 280/519 www.BDTIC.com/ST...
  • Page 281 Reserved Reset Value TIMx_CCR3 CCR3[15:0] Reserved Reset Value TIMx_CCR4 CCR4[15:0] Reserved Reset Value Reserved TIMx_DCR DBL[4:0] DBA[4:0] Reserved Reserved Reset Value TIMx_DMAR DMAB[15:0] Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 281/519 www.BDTIC.com/ST...
  • Page 282 In today’s CAN applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. Typically the number of messages in the system (and thus to be handled by each node) has significantly increased. In addition to the 282/519 www.BDTIC.com/ST...

  • Page 283: Figure 118. Can Network Topology

    Three transmit mailboxes are provided to the software for setting up messages. The transmission Scheduler decides which mailbox has to be transmitted first. 14.3.4 Acceptance filters The bxCAN provides 14 scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. 283/519 www.BDTIC.com/ST...

  • Page 284: Figure 119. Can Block Diagram

    ACK = The wait state during which hardware confirms a request by setting the INAK or SLAK bits in the CAN_MSR register SYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11 consecutive recessive bits have been monitored on CANRX 284/519 www.BDTIC.com/ST...
  • Page 285 The initialization of the filter values is independent from Initialization Mode but must be done while the filter is not active (corresponding FACTx bit cleared). The filter scale and mode configuration must be configured before entering Normal Mode. 285/519 www.BDTIC.com/ST...

  • Page 286: Figure 121. Bxcan In Silent Mode

    Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). Figure 121. bxCAN in silent mode bxCAN CANTX CANRX 286/519 www.BDTIC.com/ST...

  • Page 287: Figure 122. Bxcan In Loop Back Mode

    In order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (DLC) and the data before requesting the transmission by setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left 287/519 www.BDTIC.com/ST...
  • Page 288 At the end of the first transmission attempt, the hardware considers the request as completed and sets the RQCP bit in the CAN_TSR register. The result of the transmission is indicated in the CAN_TSR register by the TXOK, ALST and TERR bits. 288/519 www.BDTIC.com/ST...

  • Page 289: Figure 124. Transmit Mailbox States

    A received message is considered as valid when it has been received correctly according to the CAN protocol (no error until the last but one bit of the EOF field) and It passed through the identifier filtering successfully, see Section 14.5.4: Identifier filtering. 289/519 www.BDTIC.com/ST...

  • Page 290: Figure 125. Receive Fifo States

    Refer also to Section 14.5.5: Message storage Overrun Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception will lead to an overrun and a message will be lost. The hardware 290/519 www.BDTIC.com/ST...
  • Page 291 “must match” or as “don’t care”. Identifier list mode In identifier list mode, the mask registers are used as identifier registers. Thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single 291/519 www.BDTIC.com/ST...

  • Page 292: Figure 126. Filter Bank Scale Configuration - Register Organization

    Four 16-Bit Filters - Identifier List CAN_FxR0[15:8] CAN_FxR0[7:0] CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] CAN_FxR1[31:24] CAN_FxR1[23:16] Mapping STID[10:3] STID[2:0] RTR IDE EXID[17:15] x = filter bank number ID=Identifier These bits are located in the CAN_FS0R register These bits are located in the CAN_FM0R register 292/519 www.BDTIC.com/ST...

  • Page 293: Figure 127. Example Of Filter Numbering

    ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit) Deactivated ID Mask (16-bit) ID List (16-bit) ID List (32-bit) ID List (32-bit) ID Mask (32-bit) ID Mask (32-bit) ID=Identifier 293/519 www.BDTIC.com/ST...

  • Page 294: Figure 128. Filtering Mechanism - Example

    If there is no match, the incoming identifier is then compared with the filters configured in mask mode. If the identifier does not match any of the identifiers configured in the filters, the message is discarded by hardware without disturbing the software. 294/519 www.BDTIC.com/ST...

  • Page 295: Table 42. Transmit Mailbox Mapping

    The filter match index is stored in the MFMI field of the CAN_RDTxR register. The 16-bit time stamp value is stored in the TIME[15:0] field of CAN_RDTxR. Table 43. Receive mailbox mapping Offset to Receive Mailbox base Register Name address (bytes) CAN_RIxR CAN_RDTxR CAN_RDLxR CAN_RDHxR 295/519 www.BDTIC.com/ST...

  • Page 296: Figure 129. Can Error State Diagram

    To recover, bxCAN must be in normal mode. 14.5.7 Bit timing The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on the following edges. 296/519 www.BDTIC.com/ST...

  • Page 297: Figure 130. Bit Timing

    (TS2[2:0] + 1), = ( BRP[9:0] + 1 ) x t PCLK where t refers to the Time quantum = time period of the APB clock, PCLK BRP[9:0], TS1[3:0] and TS2[2:0] are defined in the CAN_BTR Register. 297/519 www.BDTIC.com/ST...

  • Page 298: Figure 131. Can Frames

    ≤ 6 • ACK = Acknowledge bit • Ctrl = Control 14.6 Interrupts Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled by means of the CAN Interrupt Enable Register (CAN_IER). 298/519 www.BDTIC.com/ST...

  • Page 299: Figure 132. Event Flags And Interrupt Generation

    The FIFO 1 interrupt can be generated by the following events: – Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’. – FIFO1 full condition, FULL1 bit in the CAN_RF1R register set. – FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set. 299/519 www.BDTIC.com/ST...
  • Page 300 14.8.1 Control and status registers CAN master control register (CAN_MCR) Address Offset: 00h Reset value: 00010002h Reserved Reserved TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ Reserved Reserved TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ 300/519 www.BDTIC.com/ST...
  • Page 301 TXFP: Transmit FIFO Priority This bit controls the transmission order when several mailboxes are pending at the Bit 2 same time. 0: Priority driven by the identifier of the message 1: Priority driven by the request order (chronologically) 301/519 www.BDTIC.com/ST...
  • Page 302 Once software has set the INRQ bit, the CAN hardware waits until the current CAN activity (transmission or reception) is completed before entering the initialization mode. Hardware signals this event by setting the INAK bit in the CAN_MSR register. 302/519 www.BDTIC.com/ST...
  • Page 303 This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this Bit 2 bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set. This bit is cleared by software. 303/519 www.BDTIC.com/ST...
  • Page 304 This bit is cleared by hardware when the CAN hardware has left the initialization mode (to be synchronized on the CAN bus). To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal. 304/519 www.BDTIC.com/ST...
  • Page 305 TERR2: Transmission Error of Mailbox 2 Bit 19 This bit is set when the previous TX failed due to an error. ALST2: Arbitration Lost for Mailbox 2 Bit 18 This bit is set when the previous TX failed due to an arbitration lost. 305/519 www.BDTIC.com/ST...
  • Page 306 TERR0: Transmission Error of Mailbox0 Bit 3 This bit is set when the previous TX failed due to an error. ALST0: Arbitration Lost for Mailbox0 Bit 2 This bit is set when the previous TX failed due to an arbitration lost. 306/519 www.BDTIC.com/ST...
  • Page 307 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ0 Bit 0 set in CAN_TI0R register). Clearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox 307/519 www.BDTIC.com/ST...
  • Page 308 These bits indicate how many messages are pending in the receive FIFO. Bits 1:0 FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit. 308/519 www.BDTIC.com/ST...
  • Page 309 These bits indicate how many messages are pending in the receive FIFO1. Bits 1:0 FMP1 is increased each time the hardware stores a new message in to the FIFO1. FMP is decreased each time the software releases the output mailbox by setting the RFOM1 bit. 309/519 www.BDTIC.com/ST...
  • Page 310 1: ERRI bit will be set when EWGF is set. Bit 7 Reserved, forced by hardware to 0. FOVIE1: FIFO Overrun Interrupt Enable Bit 6 0: No interrupt when FOVR is set. 1: Interrupt generation when FOVR is set. 310/519 www.BDTIC.com/ST...
  • Page 311 1: Interrupt generated when state of FMP[1:0] bits are not 00b. TMEIE: Transmit Mailbox Empty Interrupt Enable 0: No interrupt when RQCPx bit is set. Bit 0 1: Interrupt generated when RQCPx bit is set. Note: refer to Section 14.6: Interrupts. 311/519 www.BDTIC.com/ST...
  • Page 312 This bit is set by hardware when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127). EWGF: Error Warning Flag Bit 0 This bit is set by hardware when the warning limit has been reached (Receive Error Counter or Transmit Error Counter≥96). 312/519 www.BDTIC.com/ST...
  • Page 313 These bits define the length of a time quanta. = (BRP[9:0]+1) x t PCLK 14.8.2 Mailbox registers This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 14.5.5: Message storage on page 295 for detailed register mapping. 313/519 www.BDTIC.com/ST...
  • Page 314 The standard part of the identifier. EXID[17:0:] Extended Identifier Bit 20:3 The extended part of the identifier. IDE: Extended Identifier This bit defines the identifier type of message in the mailbox. Bit 2 0: Standard identifier. 1: Extended identifier. 314/519 www.BDTIC.com/ST...
  • Page 315 A message can contain from 0 to 8 data bytes, depending on the value in the DLC field. Mailbox data low register (CAN_TDLxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. 315/519 www.BDTIC.com/ST...
  • Page 316 Data byte 7 of the message. Bits 31:24 Note: if TGT of this message and TTCM are active, DATA7 and DATA6 will be replaced by the TIME stamp value. DATA6[7:0]: Data Byte 6 Bits 23:16 Data byte 6 of the message. 316/519 www.BDTIC.com/ST...
  • Page 317 The extended part of the identifier. IDE: Extended Identifier This bit defines the identifier type of message in the mailbox. Bit 2 0: Standard identifier. 1: Extended identifier. RTR: Remote Transmission Request Bit 1 0: Data frame 1: Remote frame Bit 0 Reserved 317/519 www.BDTIC.com/ST...
  • Page 318 Receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1) All bits of this register are write protected when the mailbox is not in empty state. Address Offsets: 1B8h, 1C8h Reset Value: xxh Note: All RX registers are write protected. DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 318/519 www.BDTIC.com/ST...
  • Page 319 Data byte 3 of the message. DATA6[7:0]: Data Byte 6 Bits 23:16 Data byte 2 of the message. DATA5[7:0]: Data Byte 5 Bits 15:8 Data byte 1 of the message. DATA4[7:0]: Data Byte 4 Bits 7:0 Data byte 0 of the message. 319/519 www.BDTIC.com/ST...
  • Page 320 All bits of this register are set and cleared by software. Reserved Reserved FINIT Bits 31:1 Reserved, forced to reset value FINIT: Filter Init Mode Initialization mode for filter banks Bit 0 0: Active filters mode. 1: Initialization mode for the filters. 320/519 www.BDTIC.com/ST...
  • Page 321 Figure 126: Filter bank scale configuration - register organization on page 292 Bits 31:14 Reserved, forced by hardware to 0. FSCx: Filter Scale Configuration These bits define the scale configuration of Filters 13-0. Bits 13:0 0: Dual 16-bit scale configuration 1: Single 32-bit scale configuration 321/519 www.BDTIC.com/ST...
  • Page 322 (CAN_FxR[0:7]), the FACTx bit must be cleared or the FINIT bit of the CAN_FMR Bits 13:0 register must be set. 0: Filter x is not active 1: Filter x is active Filter bank x registers (CAN_FxR[1:0]) (x=0..13) Address Offsets: 240h..2ACh Reset Value: xxh 322/519 www.BDTIC.com/ST...
  • Page 323 Section 14.5.4: Identifier filtering on page 291. A Mask/Identifier register in mask mode has the same bit mapping as in identifier list mode. For the register mapping/addresses of the filter banks please refer to the Table 44 on page 324. 323/519 www.BDTIC.com/ST...

  • Page 324: Table 44. Bxcan - Register Map And Reset Values

    020h-17Fh Reserved CAN_TI0R STID[10:0] EXID[17:0] 180h Reset Value CAN_TDT0R TIME[15:0] DLC[3:0] 184h Reserved Reserved Reset Value CAN_TDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 188h Reset Value CAN_TDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 18Ch Reset Value CAN_TI1R STID[10:0] EXID[17:0] 190h Reset Value 324/519 www.BDTIC.com/ST...
  • Page 325 DATA6[7:0] DATA5[7:0] DATA4[7:0] 1BCh Reset Value CAN_RI1R STID[10:0] EXID[17:0] 1C0h Reset Value CAN_RDT1R TIME[15:0] FMI[7:0] DLC[3:0] 1C4h Reserved Reset Value CAN_RDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 1C8h Reset Value CAN_RDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 1CCh Reset Value 1D0h-1FFh Reserved 325/519 www.BDTIC.com/ST...
  • Page 326 21Ch Reserved Reset Value 220h Reserved 224-23Fh Reserved CAN_F0R0 FB[31:0] 240h Reset Value CAN_F0R1 FB[31:0] 244h Reset Value CAN_F1R0 FB[31:0] 248h Reset Value CAN_F1R1 FB[31:0] 24Ch Reset Value CAN_F13R0 FB[31:0] 2A8h Reset Value CAN_F13R1 FB[31:0] 2ACh Reset Value 326/519 www.BDTIC.com/ST...
  • Page 327 Detection of misplaced start or stop condition – Overrun/Underrun if clock stretching is disabled 2 Interrupt vectors: – 1 Interrupt for successful address/ data communication – 1 Interrupt for error condition Optional Clock Stretching 1-byte buffer with DMA capability 327/519 www.BDTIC.com/ST...
  • Page 328 (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to the following figure. 328/519 www.BDTIC.com/ST...

  • Page 329: Figure 133. I2C Bus Protocol

    Acknowledge may be enabled or disabled by software. The I C interface addresses (dual addressing 7-bit/ 10-bit and/or general call address) can be selected by software. The Block Diagram of the I C interface is shown in Figure 134. 329/519 www.BDTIC.com/ST...

  • Page 330: Figure 134. I2C Block Diagram

    PEC REGISTER CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTERS (CR1&CR2) CONTROL STATUS REGISTERS LOGIC (SR1&SR2) SMBALERT INTERRUPTS DMA REQUESTS & ACK Note: SMBALERT is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled. 330/519 www.BDTIC.com/ST...
  • Page 331 It will enter Transmitter mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). The TRA bit indicates whether the slave is in Receiver or Transmitter mode. 331/519 www.BDTIC.com/ST...

  • Page 332: Figure 135. Transfer Sequence Diagram For Slave Transmitter

    EV1: ADDR=1, cleared by reading SR1 followed by reading SR2 EV3-1: TxE=1, shift register empty. EV3: TxE=1, cleared by writing DR; shift register not empty EV3-2: AF=1; AF is cleared by writing ‘0’ in AF bit of SR1 register. 332/519 www.BDTIC.com/ST...

  • Page 333: Figure 136. Transfer Sequence Diagram For Slave Receiver

    The STOPF bit and generates an interrupt if the ITEVFEN bit is set. Then the interface waits for a read of the SR1 register followed by a write to the CR1 register (see Figure 136 Transfer sequencing EV4). 333/519 www.BDTIC.com/ST...
  • Page 334 The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set. Then the master waits for a read of the SR1 register followed by a read of the SR2 register (see Figure 137 & Figure 138 Transfer sequencing). 334/519 www.BDTIC.com/ST...
  • Page 335 ITBUFEN bits are set. If TxE is set and a data byte was not written in the DR register before the end of the last data transmission, BTF is set and the interface waits until BTF is cleared. 335/519 www.BDTIC.com/ST...

  • Page 336: Figure 137. Transfer Sequence Diagram For Master Transmitter

    EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2. EV8_1: TxE=1 shift register empty EV8: TxE=1 cleared by writing DR register. EV8_2: TxE=1, BTF = 1 cleared by HW by stop condition EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register. 336/519 www.BDTIC.com/ST...

  • Page 337: Figure 138. Transfer Sequence Diagram For Master Receiver

    CR2 with START = 1. EV7: RxNE=1 cleared by reading DR register. EV7_1: RxNE=1 cleared by reading DR register, program ACK=0 and STOP request EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register. 337/519 www.BDTIC.com/ST...
  • Page 338 The same byte in the DR register will be sent again The user should make sure that data received on the receiver side during an underrun error is discarded and that the next bytes are written within the clock low time specified in the I C bus standard. 338/519 www.BDTIC.com/ST...

  • Page 339: Table 45. Smbus Vs I2C

    Table 45. SMBus vs I SMBus Max. speed 100 kHz Max. speed 400 kHz Min. clock speed 10 kHz No minimum clock speed 35 ms clock low time-out No time-out Logic levels are fixed Logic levels are VDD dependent 339/519 www.BDTIC.com/ST...
  • Page 340 SMBALERT is a wired-AND signal just as the SCL and SDA signals are. SMBALERT is used in conjunction with the SMBus General Call Address. Messages invoked with the SMBus are 2 bytes long. 340/519 www.BDTIC.com/ST...
  • Page 341 DMA requests (when enabled) are generated only for data transfer. DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception. When the number of data transfers which has been programmed for the 341/519 www.BDTIC.com/ST...
  • Page 342 Set the I2C_DR register address in DMA_CPARx register. The data will be moved from this address to the memory after each RxNE event. Set the memory address in the DMA_CMARx register. The data will be loaded from the I2C_DR register to this memory area after each RxNE event. 342/519 www.BDTIC.com/ST...
  • Page 343 (LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA request for a master receiver, a NACK is automatically sent after the last received byte. PEC calculation is corrupted by an arbitration loss. 343/519 www.BDTIC.com/ST...

  • Page 344: Table 46. I2C Interrupt Requests

    Timeout/Tlow error TIMEOUT SMBus Alert SMBALERT Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt channel. BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the same interrupt channel. 344/519 www.BDTIC.com/ST...

  • Page 345: Figure 139. I2C Interrupt Mapping Diagram

    15.6 I2C register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 15.6.1 Control register 1(I2C_CR1) Address offset: 00h Reset Value: 0000h Res. ALERT STOP START ENGC Res. STRETCH TYPE 345/519 www.BDTIC.com/ST...
  • Page 346 Bit 9 In Slave mode: 0: No Stop generation. 1: Release the SCL and SDA lines after the current byte transfer. Note: In Master mode, the BTF bit of the I2C_SR1 register must be cleared when STOP is requested. 346/519 www.BDTIC.com/ST...
  • Page 347 IDLE state. All bit resets due to PE=0 occur at the end of the communication. In master mode, this bit must not be reset before the end of the communication. 347/519 www.BDTIC.com/ST...
  • Page 348 1: Error interrupt enabled This interrupt is generated when: – BERR = 1 Bit 8 – ARLO = 1 – AF = 1 – OVR = 1 – PECERR = 1 – TIMEOUT = 1 – SMBAlert = 1 348/519 www.BDTIC.com/ST...
  • Page 349 ADD0: Interface Address Bit 0 7-bit addressing mode: don’t care 10-bit addressing mode: bit 0 of address 15.6.4 Own address register 2 (I2C_OAR2) Address offset: 0Ch Reset Value: 0000h Reserved ADD2[7:1] ENDUAL Bits 15:8 Reserved, forced by hardware to 0. 349/519 www.BDTIC.com/ST...
  • Page 350 1. In slave mode, the address is not copied into DR. 2. Write collision is not managed (DR can be written if TxE=0). If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so cannot be read. 350/519 www.BDTIC.com/ST...
  • Page 351 The same byte is sent twice. – Cleared by software writing 0, or by hardware when PE=0. Note: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a hold timing error occurs 351/519 www.BDTIC.com/ST...
  • Page 352 Bit 4 after an acknowledge (if ACK=1). – Cleared by software reading the SR1 register followed by a write in the CR1 register, or by hardware when PE=0 Note: The STOPF bit is not set after a NACK reception 352/519 www.BDTIC.com/ST...
  • Page 353 SB: Start Bit (Master mode). 0: No Start condition 1: Start condition generated. Bit 0 – Set when a Start condition generated. – Cleared by software by reading the SR1 register followed by writing the DR register, or by hardware when PE=0 353/519 www.BDTIC.com/ST...
  • Page 354 This bit is set depending on R/W bit of address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0. 354/519 www.BDTIC.com/ST...
  • Page 355 Bit 0 – Set by hardware as soon as the interface is in Master mode (SB=1). – Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1), or by hardware when PE=0. 355/519 www.BDTIC.com/ST...
  • Page 356 1. The minimum allowed value is 04h, except in FAST DUTY mode where the minimum allowed value is 01h 2. t includes the SCLH rising edge high 3. t includes the SCLH falling edge 4. These timings are without filters. 356/519 www.BDTIC.com/ST...
  • Page 357 The filter value can also be added to TRISE[5:0]. If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order to respect the t parameter. HIGH Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0). 357/519 www.BDTIC.com/ST...

  • Page 358: Table 47. I2C Register Map And Reset Values

    Reset Value I2C_DR DR[7:0] Reserved Reset Value I2C_SR1 Reserved Reset Value I2C_SR2 PEC[7:0] Reserved Reset Value I2C_CCR CCR[11:0] Reserved Reset Value I2C_TRISE TRISE[5:0] Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 358/519 www.BDTIC.com/ST...
  • Page 359 CRC value can be transmitted as last byte in Tx mode – Automatic CRC error checking for last received byte in full duplex mode Master mode fault, overrun and CRC error flags with interrupt capability 1-byte transmission and reception buffer with DMA capability: Tx and Rx requests 359/519 www.BDTIC.com/ST...

  • Page 360: Figure 140. Spi Block Diagram

    Master NSS pin see a low level become slaves when they are configured in NSS hardware mode. A basic example of interconnections between a single master and a single slave is illustrated in Figure 141. 360/519 www.BDTIC.com/ST...

  • Page 361: Figure 141. Single Master/ Single Slave Application

    This bit affects both master and slave modes. If CPOL is reset, SCK pin has a low level idle state. If CPOL is set, SCK pin has a high level idle state. 361/519 www.BDTIC.com/ST...
  • Page 362 The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). The Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register, and determines the data length during transmission/reception. 362/519 www.BDTIC.com/ST...

  • Page 363: Figure 143. Data Clock Timing Diagram

    16.3.2 SPI slave mode In slave configuration, the serial clock is received on the SCK pin from the master device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer rate. 363/519 www.BDTIC.com/ST...
  • Page 364 Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format If the NSS pin is required in input mode, in Hardware mode, connect the NSS pin to a high level signal during the complete byte transmit sequence. In software mode, set the 364/519 www.BDTIC.com/ST...
  • Page 365 Receive-only mode. When the RXONLY bit is reset, the SPI will function in full duplex mode. Receive-only mode To start the communication in receive-only mode, it is necessary to enable the SPI. In the master mode, the communication starts immediately and will stop when the SPE bit is reset 365/519 www.BDTIC.com/ST...
  • Page 366 CRC registers (SPI_RXCRCR and SPI_TXCRCR). In full-duplex mode, the CRC is automatically verified. However, in simplex mode, CRC verification is performed through software by the receiver. Note: Please refer to the product specs for availability of this feature. 366/519 www.BDTIC.com/ST...
  • Page 367 DMA capability with CRC (full-duplex mode) When the SPI communication is enabled with the CRC communication along with the DMA mode, the transmission and reception of the CRC bytes at the end of communication is done automatically in full-duplex mode. 367/519 www.BDTIC.com/ST...
  • Page 368 A read to the SPI_DR register returns this byte. All other subsequently transmitted bytes are lost. Clearing the OVR bit is done by a read of the SPI_DR register followed by a read access to the SPI_SR register. 368/519 www.BDTIC.com/ST...

  • Page 369: Table 48. Spi Interrupt Requests

    In master mode, the MOSI pin is used and in slave mode, MISO pin is used. CRCEN: Hardware CRC calculation enable 0: CRC calculation disabled Bit 13 1: CRC calculation Enabled Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation 369/519 www.BDTIC.com/ST...
  • Page 370 111: f /256 Note: These bits should not be changed when the communication is ongoing. MSTR: Master Selection 0: Slave configuration Bit 2 1: Master configuration Note: This bit should not be changed when the communication is ongoing. 370/519 www.BDTIC.com/ST...
  • Page 371 CPHA: Clock Phase 0: The first clock transition is the first data capture edge Bit 0 1: The second clock transition is the first data capture edge Note: This bit should not be changed when the communication is ongoing. 371/519 www.BDTIC.com/ST...
  • Page 372 1: Tx buffer DMA enabled RXDMAEN: Rx Buffer DMA Enable When this bit is set, the DMA request is made whenever the RXNE flag is Bit 0 set. 0: Rx buffer DMA disabled 1: Rx buffer DMA enabled 372/519 www.BDTIC.com/ST...
  • Page 373 Bit 3:2 Reserved. Forced to 0 by hardware. TXE: Transmit buffer empty Bit 1 0: Tx buffer not empty 1: Tx buffer empty RXNE: Receive buffer not empty Bit 0 0: Rx buffer empty 1: Rx buffer not empty 373/519 www.BDTIC.com/ST...
  • Page 374 This register contains the polynomial for the CRC calculation. Bits 15:0 The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required. 16.4.6 SPI Rx CRC register (SPI_RXCRCR) Address Offset: 14h Reset Value: 0000 0000 (0000h) RxCRC[15:0] 374/519 www.BDTIC.com/ST...
  • Page 375 (DFF bit of the SPI_CR1 register is set). CRC calculation is done based on CRC16 - CCITT standard. Note: A read to this register when the BSY flag is set could return a incorrect value 375/519 www.BDTIC.com/ST...

  • Page 376: Table 49. Spi Register Map And Reset Values

    Reset Value SPI_SR Reserved Reset Value SPI_DR DR[15:0] Reserved Reset Value SPI_CRCPR CRCPOLY[15:0] Reserved Reset Value SPI_RXCRCR RxCRC[15:0] Reserved Reset Value SPI_TXCRCR TxCRC[15:0] Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 376/519 www.BDTIC.com/ST...
  • Page 377 It supports synchronous one-way communication and half-duplex single wire communication. It also supports the LIN (Local Interconnection Network), Smartcard Protocol and IrDA (Infrared Data Association) SIR ENDEC specifications, and modem operations (CTS/RTS). It allows multi-processor communication. 377/519 www.BDTIC.com/ST...
  • Page 378 – Noise error – Frame error – Parity error Ten interrupt sources with flags: – CTS changes – LIN break detection – Transmit data register empty – Transmission complete – Receive data register full – Idle line received 378/519 www.BDTIC.com/ST...
  • Page 379 RX. This can be used to control peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity are software programmable. In smartcard mode, SCLK can provide the clock to the smartcard. Following pins are required to interface in IrDA mode. 379/519 www.BDTIC.com/ST...
  • Page 380 Following pins are required in modem mode: nCTS: Clear To Send blocks the data transmission at the end of the current transfer when high nRTS: Request to send indicates that the USART is ready to receive a data (when low). 380/519 www.BDTIC.com/ST...

  • Page 381: Figure 144. Usart Block Diagram

    WAKE TRANSMIT CLOCK RECEIVER CONTROL CONTROL UNIT RXNE IDLE CTS LBD TXE TC RXNE IDLE ORE NE FE TXEIE TCIE USART INTERRUPT CONTROL USART_BRR TRANSMITTER RATE TRANSMITTER CONTROL CLOCK BRR (Mantissa) RECEIVER RATE CONTROL CONVENTIONAL BAUD RATE GENERATOR 381/519 www.BDTIC.com/ST...

  • Page 382: Figure 145. Word Length Programming

    8-bit Word length (M bit is reset), 1 stop bit Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** Start Idle Frame Start Break Frame Extra ’1’ ** LBCL bit controls last data clock pulse 382/519 www.BDTIC.com/ST...
  • Page 383 A break transmission will be 10 low bits followed by the configured number of stop bits (when m = 0) and 11 low bits followed by the configured number of stop bits (when m = 1). It is not possible to transmit long breaks (break of length greater than 10/11 low bits). 383/519 www.BDTIC.com/ST...

  • Page 384: Figure 146. Configurable Stop Bits

    This flag generates an interrupt if the TXEIE bit is set. When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. 384/519 www.BDTIC.com/ST...
  • Page 385 Configure the DMA register as explained in multi-buffer communication. STEP 3 Select the desired baud rate using the baud rate register USART_BRR Set the RE bit USART_CR1. This enables the receiver which begins searching for a start bit. 385/519 www.BDTIC.com/ST...
  • Page 386 RDR. This case can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received. It may also occur when the 386/519 www.BDTIC.com/ST...

  • Page 387: Table 50. Noise Detection From Sampled Data

    The NE bit is reset by a USART_SR register read operation followed by a USART_DR register read operation. Framing error A framing error is detected when: The stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. 387/519 www.BDTIC.com/ST...
  • Page 388 -Input clock to the peripheral USARTDIV is an unsigned fixed point number. The 12-bit mantissa is coded on the USART_BRR register. How to derive USARTDIV from BRR register values: Example 1: If DIV_Mantissa = 27d and DIV_Fraction= 12d (BRR=1BCh), then 388/519 www.BDTIC.com/ST...
  • Page 389 DIV_Mantissa = mantissa (50.990d) = 50d = 32h Note: The Baud Counters will be updated with the new value of the Baud Registers after a write to BRR. Hence the Baud Register value should not be changed during a transaction. 389/519 www.BDTIC.com/ST...

  • Page 390: Table 51. Error Calculation For Programmed Baud Rates

    It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the USART_SR register. RWU can also be written to 0 by software. An example of mute mode behavior using idle line detection is given in Figure 148. 390/519 www.BDTIC.com/ST...

  • Page 391: Figure 148. Mute Mode Using Idle Line Detection

    Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table 391/519 www.BDTIC.com/ST...

  • Page 392: Table 52. Frame Formats

    When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a start signal. The method for detecting start bits is the same when searching break 392/519 www.BDTIC.com/ST...
  • Page 393 Figure 150: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 394. Examples of break frames are given on Figure 151: Break detection in LIN mode vs Framing error detection on page 395. 393/519 www.BDTIC.com/ST...

  • Page 394: Figure 150. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)

    Case 3: break signal long enough => break detected, LBD is set “Short” Break Frame RX line Capture Strobe Break State machine Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 wait delimiter Idle Read Samples 394/519 www.BDTIC.com/ST...

  • Page 395: Figure 151. Break Detection In Lin Mode Vs Framing Error Detection

    (which depends on the baud rate: 1/16 bit time). Note: The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR 395/519 www.BDTIC.com/ST...

  • Page 396: Figure 152. Usart Example Of Synchronous Transmission

    M=0 (8 data bits) Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop Start Data on RX (from slave) Capture Strobe * LBCL bit controls last data clock pulse 396/519 www.BDTIC.com/ST...

  • Page 397: Figure 154. Usart Data Clock Timing Diagram (M=1)

    (or output high open-drain) when not driven by the USART. Apart from this, the communications are similar to what is done in normal USART mode. The conflicts on the line must be managed by the software (by the use of a centralized 397/519 www.BDTIC.com/ST...

  • Page 398: Figure 156. Iso 7816-3 Asynchronous Protocol

    1/2 stop bit period. This is to indicate to the Smartcard that the data transmitted to USART has not been correctly received. This 398/519 www.BDTIC.com/ST...

  • Page 399: Figure 157. Parity Error Detection Using The 1.5 Stop Bits

    SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. The division ratio is configured in the prescaler register USART_GTPR. SCLK frequency can be programmed from f /2 to /62, where f is the peripheral input clock. 399/519 www.BDTIC.com/ST...
  • Page 400 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode programmable divisor divides the system clock to achieve this value. 400/519 www.BDTIC.com/ST...

  • Page 401: Figure 158. Irda Sir Endec- Block Diagram

    Rx buffer and Tx buffer are generated independently. Note: You should refer to product specs for availability of the DMA controller. If DMA is not available in the product, you should use the USART as explained in Section 17.2.3 401/519 www.BDTIC.com/ST...
  • Page 402 DMA channel interrupt vector. The DMAR bit should be cleared by software in the USART_CR3 register during the interrupt subroutine. Note: If DMA is used for reception, do not enable the RXNEIE bit. 402/519 www.BDTIC.com/ST...

  • Page 403: Figure 160. Hardware Flow Control Between 2 Usart

    Data 2 can now be transmitted CTS flow control If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is 403/519 www.BDTIC.com/ST...

  • Page 404: Figure 162. Cts Flow Control

    Figure 162. CTS flow control nCTS Transmit data register Data 2 empty Data 3 empty Start Stop Stop Idle Start Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until nCTS = 0 404/519 www.BDTIC.com/ST...

  • Page 405: Table 53. Usart Interrupt Requests

    Framing Error (only in multi buffer communication). These events generate an interrupt if the corresponding Enable Control Bit is set. Figure 163. USART interrupt mapping diagram TCIE TXEIE CTSIE USART IDLE interrupt IDLEIE RXNEIE RXNEIE RXNE PEIE LBDIE DMAR 405/519 www.BDTIC.com/ST...
  • Page 406 An interrupt is generated if TCIE=1 in the USART_CR1 register. It is Bit 6 cleared by a software sequence (an read to the USART_SR register followed by a write to the USART_DR register). 0: Transmission is not complete 1: Transmission is complete 406/519 www.BDTIC.com/ST...
  • Page 407 This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupting interrupt is generated on NE flag in case of Multi Buffer communication if the EIE bit is set. 407/519 www.BDTIC.com/ST...
  • Page 408 (a read to the status register followed by a read Bit 0 to the USART_DR data register). An interrupt is generated if PEIE=1 in the USART_CR1 register. 0: No parity error 1: Parity error 408/519 www.BDTIC.com/ST...
  • Page 409 17.4.3 Baud rate register (USART_BRR) Note: The baud counters stop counting if the TE or RE bits are disabled respectively. Address Offset: 08h Reset Value: 0000h Reserved DIV_Mantissa[11:0] DIV_Fraction[3:0] Bits 31:16 Reserved, forced by hardware to 0. 409/519 www.BDTIC.com/ST...
  • Page 410 M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set Bit 10 and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled 410/519 www.BDTIC.com/ST...
  • Page 411 2: When TE is set there is a 1 bit-time delay before the transmission starts. RE: Receiver Enable. This bit enables the receiver. It is set and cleared by software. Bit 2 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit 411/519 www.BDTIC.com/ST...
  • Page 412 This bit set is used to send break characters. It can be set and cleared by software. It should be set by software, and will be reset by hardware during the Bit 0 stop bit of break. 0: No break character is transmitted 1: Break character will be transmitted 412/519 www.BDTIC.com/ST...
  • Page 413 It works in conjunction with the CPOL bit to produce the Bit 9 desired clock/data relationship (see figures to 155) 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first data capture edge. 413/519 www.BDTIC.com/ST...
  • Page 414 This bit-field gives the address of the USART node. Bits 3:0 This is used in multi-processor communication during mute mode, for wake up with address mark detection. Note: These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled. 414/519 www.BDTIC.com/ST...
  • Page 415 This bit is used for enabling Smartcard mode. Bit 5 0: Smartcard Mode disabled 1: Smartcard Mode enabled NACK: Smartcard NACK enable. Bit 4 0: NACK transmission in case of parity error is disabled 1: NACK transmission during parity error is enabled. 415/519 www.BDTIC.com/ST...
  • Page 416 USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the Bit 0 USART_CR3 register). 0: Interrupt is inhibited 1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and FE=1 or ORE=1 or NE=1 in the USART_SR register. 416/519 www.BDTIC.com/ST...
  • Page 417 00000: Reserved - do not program this value 00001: divides the source clock by 2 00010: divides the source clock by 4 00011: divides the source clock by 6 Note: 1: Bits [7:5] have no effect if Smartcard mode is used. 417/519 www.BDTIC.com/ST...

  • Page 418: Table 54. Usart Register Map And Reset Values

    DIV_Mantissa[15:4] [3:0] Reserved Reset Value USART_CR1 Reserved Reset Value STOP USART_CR2 ADD[3:0] [1:0] Reserved Reset Value USART_CR3 Reserved Reset Value USART_GTPR GT[7:0] PSC[7:0] Reserved Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 418/519 www.BDTIC.com/ST...
  • Page 419 Cyclic Redundancy Check (CRC) generation/checking, Non-Return-to-Zero Inverted (NRZI) encoding/decoding and bit-stuffing Isochronous transfers support Double-buffered bulk/isochronous endpoint support USB Suspend/Resume operations Frame locked clock pulse generation 18.3 Block diagram Figure 164 shows the block diagram of the USB Peripheral. 419/519 www.BDTIC.com/ST...

  • Page 420: Figure 164. Usb Peripheral Block Diagram

    Transaction formatting is performed by the hardware, including CRC generation and checking. Each endpoint is associated with a buffer description block indicating where the endpoint related memory area is located, how large it is or how many bytes must be transmitted. 420/519 www.BDTIC.com/ST...
  • Page 421 Endpoint-Related Registers: Each endpoint has an associated register containing the endpoint type and its current status. For mono-directional/single-buffer endpoints, a single register can be used to implement two distinct endpoints. The number of registers is 8, allowing up to 16 mono-directional/single-buffer or up to 7 double-buffer 421/519 www.BDTIC.com/ST...
  • Page 422 Upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the USB Peripheral and subsequently de-assert its reset signal so to be able to access its registers. The whole initialization sequence is hereafter described. 422/519 www.BDTIC.com/ST...
  • Page 423 USB standard at 48 MHz, and this can be different from the clock used for the interface to the APB1 bus. Different clock configurations are possible where the APB1 clock frequency can be higher or lower than the USB Peripheral one. 423/519 www.BDTIC.com/ST...
  • Page 424 (Refer to Section 18.5.4: Isochronous transfers Section 18.5.3: Double-buffered endpoints respectively). The relationship between buffer description table entries and packet buffer areas is depicted in Figure 165. 424/519 www.BDTIC.com/ST...

  • Page 425: Figure 165. Packet Buffer Areas With Examples Of Buffer Description Table Locations

    The USB Peripheral will never change the contents of memory locations adjacent to the allocated memory buffers; if a packet bigger than the allocated buffer length is received (buffer overrun condition) the data will be copied to the memory only up to the last available location. 425/519 www.BDTIC.com/ST...
  • Page 426 It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second IN transaction addressed to the same endpoint immediately following the one which triggered the CTR interrupt. 426/519 www.BDTIC.com/ST...
  • Page 427 It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second OUT transaction addressed to the same endpoint following immediately the one which triggered the CTR interrupt. 427/519 www.BDTIC.com/ST...
  • Page 428 SETUP token again. This is done to avoid losing the notification of a SETUP transaction addressed to the same endpoint immediately following the transaction, which triggered the CTR_RX interrupt. 428/519 www.BDTIC.com/ST...
  • Page 429 This new buffer flag is called SW_BUF. In the following table the correspondence between register bits and DTOG/SW_BUF definition is explained, for the cases of ‘transmission’ and ‘reception’ double-buffered bulk endpoints. 429/519 www.BDTIC.com/ST...

  • Page 430: Table 55. Double-Buffering Buffer Flag Definition

    Unlike common transactions, and the first one after DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value remains ‘11’ (Valid). However, as the token packet of a new transaction is received, the actual endpoint status will 430/519 www.BDTIC.com/ST...
  • Page 431 Packet buffer used by the Type value USB Peripheral application software ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1 buffer description table buffer description table locations. locations. ADDRn_TX_1 / COUNTn_TX_1 ADDRn_TX_0 / COUNTn_TX_0 buffer description table buffer description table locations. locations. 431/519 www.BDTIC.com/ST...
  • Page 432 SUSP notification of the USB Peripheral: Set the FSUSP bit in the register to 1. This action activates the suspend mode within the USB Peripheral. As soon as the suspend mode is activated, the check on SOF 432/519 www.BDTIC.com/ST...

  • Page 433: Table 58. Resume Event Detection

    ‘1’ and resetting it to 0 after an interval between 1mS and 15mS (this interval can be timed using ESOF interrupts, occurring with a 1mS period when the system clock is running at nominal frequency). Once the RESUME bit is clear, the resume sequence will be 433/519 www.BDTIC.com/ST...
  • Page 434 1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the register is set. ERRM: Error Interrupt Mask 0: ERR Interrupt disabled. Bit 13 1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the register is set. 434/519 www.BDTIC.com/ST...
  • Page 435 USB suspend condition. The USB activity during the suspend mode (WKUP event) asynchronously resets this bit (it can also be reset by software). 0: No Low-power mode. 1: Enter Low-power mode. 435/519 www.BDTIC.com/ST...
  • Page 436 ‘0’ (these bits can only be cleared by software). Read-modify-write cycles should be avoided because between the read and the write operations another bit could be set by the hardware and the next write will clear it before the microprocessor has the time to serve the event. 436/519 www.BDTIC.com/ST...
  • Page 437 USB reset and it is disabled by the hardware when the suspend mode is active (FSUSP=1) until the end of resume sequence. This bit is read/write but only ‘0’ can be written and writing ‘1’ has no effect. 437/519 www.BDTIC.com/ST...
  • Page 438 EP0R having the highest priority followed by EP1R and so on. The application software can assign a register to each endpoint according to this priority scheme, so as to order the concurring endpoint requests in a suitable way. These bits are read only. 438/519 www.BDTIC.com/ST...
  • Page 439 This bit field contains the 11-bits frame number contained in the last received SOF Bits 10:0 packet. The frame number is incremented for every frame sent by the host and it is useful for Isochronous transfers. This bit field is updated on the generation of an SOF interrupt. 439/519 www.BDTIC.com/ST...
  • Page 440 (Refer to Structure and usage of packet buffers on page 423). Bits 2:0 Reserved, forced by hardware to 0. 440/519 www.BDTIC.com/ST...
  • Page 441 ‘invariant’ value that must be used whenever their modification is not required. It is recommended to modify these registers with a load instruction where all the bits, which can be modified only by the hardware, are written with their ‘invariant’ value. 441/519 www.BDTIC.com/ST...
  • Page 442 To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while CTR_RX bit is at 1; its state changes when CTR_RX is at 0. This bit is read-only. 442/519 www.BDTIC.com/ST...
  • Page 443 A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only ‘0’ can be written. 443/519 www.BDTIC.com/ST...

  • Page 444: Table 59. Reception Status Encoding

    DISABLED: all reception requests addressed to this endpoint are ignored. STALL: the endpoint is stalled and all reception requests result in a STALL handshake. NAK: the endpoint is naked and all reception requests result in a NAK handshake. VALID: this endpoint is enabled for reception. 444/519 www.BDTIC.com/ST...

  • Page 445: Table 60. Endpoint Type Encoding

    DISABLED: all transmission requests addressed to this endpoint are ignored. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is naked and all transmission requests result in a NAK handshake. VALID: this endpoint is enabled for transmission. 445/519 www.BDTIC.com/ST...
  • Page 446 COUNTn_TX[9:0]: Transmission Byte Count Bits 9:0 These bits contain the number of bytes to be transmitted by the endpoint associated with the register at the next IN token addressed to it. Double-buffered and Isochronous IN Endpoints have two COUNTn_TX_1[9:0] COUNTn_TX_0[9:0] 446/519 www.BDTIC.com/ST...
  • Page 447 OUT/SETUP token addressed to it. This bit must always be written as ‘0’ since packet memory is word-wide and all packet Bit 0 buffers must be word-aligned. 447/519 www.BDTIC.com/ST...
  • Page 448 Bits 9:0 These bits contain the number of bytes received by the endpoint associated with the register during the last OUT/SETUP transaction addressed to it. Double-buffered and Isochronous OUT Endpoints have two BLSIZE NUM_BLOCK_1[4:0] COUNTn_RX_1[9:0] BLSIZE NUM_BLOCK_0[4:0] COUNTn_RX_0[9:0] 448/519 www.BDTIC.com/ST...

  • Page 449: Table 63. Definition Of Allocated Buffer Memory

    2 (‘00010’) 4 bytes 96 bytes 3 (‘00011’) 6 bytes 128 bytes 15 (‘01111’) 30 bytes 512 bytes 16 (‘10000’) 32 bytes 17 (‘10001’) 34 bytes 18 (‘10010’) 36 bytes 30 (‘11110’) 60 bytes 31 (‘11111’) 62 bytes 449/519 www.BDTIC.com/ST...

  • Page 450: Table 64. Usb Register Map And Reset Values

    Reserved Reserved Reserved Reset Value EP_ID[3:0] Reserved Reset Value LSOF FN[10:0] [1:0] Reserved Reset Value ADD[6:0] Reserved Reserved Reset Value BTABLE[15:3] Reserved Reserved Reset Value Note: Refer to Table 1 on page 27 for the register boundary addresses. 450/519 www.BDTIC.com/ST...
  • Page 451 ≤ V ADC input range: V REF- REF+ DMA request generation during regular channel conversion The block diagram of the ADC is shown in Figure 166. Note: ,if available (depending on package), must be tied to VSSA. REF- 451/519 www.BDTIC.com/ST...

  • Page 452: Figure 166. Single Adc Block Diagram

    16 REGULAR ADC_IN15 CHANNELS Temp. sensor REFINT From ADC prescaler JEXTSEL[2:0] bits TIM1_TRGO TIM1_CH4 JEXTRIG TIM2_TRGO TIM2_CH1 Start trigger TIM3_CH4 EXTRIG (injected group) TIM4_TRGO EXTI_15 EXTSEL[2:0] bits TIM1_CH1 TIM1_CH2 Start trigger TIM1_CH3 (regular group) TIM2_CH2 TIM3_TRGO TIM4_CH4 EXTI_11 452/519 www.BDTIC.com/ST...
  • Page 453 The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register. The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. 453/519 www.BDTIC.com/ST...
  • Page 454 If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – An interrupt is generated if the JEOCIE bit is set. 454/519 www.BDTIC.com/ST...

  • Page 455: Figure 167. Timing Diagram

    ADC_CR2 register. The comparison is done before the alignment (see Section 19.6). The analog watchdog can be enabled one or more channels by configuring the ADC_CR1 register as shown in Table 66. Figure 168. Analog watchdog guarded area Analog voltage High threshold Guarded area Low threshold 455/519 www.BDTIC.com/ST...

  • Page 456: Table 66. Analog Watchdog Channel Selection

    If the DMA bit is set, the direct memory access controller is used to transfer the converted data of regular group channels to SRAM after each EOC. The injected channel converted data is always stored in the ADC_JDRx registers. 456/519 www.BDTIC.com/ST...

  • Page 457: Figure 169. Injected Conversion Latency

    When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register. 457/519 www.BDTIC.com/ST...
  • Page 458 In the example above, the 4th trigger reconverts the 1st injected channel It is not possible to use both auto-injected and discontinuous modes simultaneously. The user must avoid setting discontinuous mode for both regular and injected groups together. Discontinuous mode must be enabled only for one group conversion. 458/519 www.BDTIC.com/ST...

  • Page 459: Figure 170. Calibration Timing Diagram

    Before starting a calibration the ADC must have been in power-off state (ADON bit = ‘0’) for at least two ADC clock cycles. Figure 170. Calibration timing diagram Calibration Reset by Hardware Calibration ongoing Normal ADC Conversion Conversion 459/519 www.BDTIC.com/ST...

  • Page 460: Figure 171. Right Alignment Of Data

    SEL[2:0] and JEXTSEL[2:0] control bit allow the application to select decide which out of 8 possible events can trigger conversion for the regular and injected groups. Note: When an external trigger is selected for ADC regular or injected conversion, only the rising edge of the signal can start the conversion. 460/519 www.BDTIC.com/ST...

  • Page 461: Table 67. External Trigger For Regular Channels

    ADC_DR register. Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user. 461/519 www.BDTIC.com/ST...
  • Page 462 Injected simultaneous mode + Interleaved mode Note: In dual ADC mode, to read the slave converted data on the master data register, the DMA bit must be enabled even if it is not used to transfer converted regular channel data. 462/519 www.BDTIC.com/ST...

  • Page 463: Figure 173. Dual Adc Block Diagram

    Note: External triggers are present on ADC2 but are not shown for the purposes of this diagram * In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over the entire 32 bits. 463/519 www.BDTIC.com/ST...

  • Page 464: Figure 174. Injected Simultaneous Mode On 4 Channels

    An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when ADC1/ADC2 regular channels are all converted. Figure 175. Regular simultaneous mode on 16 channels Sampling Conversion ADC1 CH15 ADC2 CH15 CH14 CH13 CH12 End of conversion on ADC1 and ADC2 Trigger 464/519 www.BDTIC.com/ST...

  • Page 465: Figure 176. Fast Interleaved Mode On 1 Channel In Continuous Conversion Mode

    A new ADC2 start is automatically generated after 28 ADC clock cycles CONT bit can not be set in the mode since it continuously converts the selected regular channel. Note: The application must ensure that no external trigger for injected channel occurs when interleaved mode is enabled. 465/519 www.BDTIC.com/ST...

  • Page 466: Figure 177. Slow Interleaved Mode On 1 Channel

    A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts. 466/519 www.BDTIC.com/ST...

  • Page 467: Figure 179. Alternate Trigger: 4 Injected Channels (Each Adc) In Discontinuous Model

    ADC2 reg ADC2 inj synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored. Figure 181 shows the behavior in this case (2nd trig is ignored). 467/519 www.BDTIC.com/ST...

  • Page 468: Figure 181. Case Of Trigger Occurring During Injected Conversion

    When not in use, this sensor can be put in power down mode. Note: The TSVREFE bit must be set to enable both internal channels: ADC_IN16 (temperature sensor) and ADC_IN17 (V ) conversion. REFINT Main features Supported Temperature Range: -40 to 125 degrees Precision: +/- 1.5° C 468/519 www.BDTIC.com/ST...

  • Page 469: Figure 183. Temperature Sensor And Vrefint Channel Block Diagram

    ADON and TSVREFE bits should be set at the same time. 19.12 Interrupts An interrupt can be produced on end of conversion for regular and injected groups and when the Analog Watchdog status bit is set. Separate interrupt enable bits are available for flexibility. 469/519 www.BDTIC.com/ST...

  • Page 470: Table 69. Adc Interrupts

    End of Conversion regular group EOCIE End of Conversion injected group JEOC JEOCIE Analog Watchdog Status bit is set AWDIE 19.13 ADC register description Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions. 470/519 www.BDTIC.com/ST...
  • Page 471 This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by Bit 0 software. 0: No Analog Watchdog event occurred 1: Analog Watchdog event occurred 471/519 www.BDTIC.com/ST...
  • Page 472 1001: Alternate trigger mode only Notes: –These bits are reserved in ADC2. –In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. 472/519 www.BDTIC.com/ST...
  • Page 473 This bit is set and cleared by software to enable/disable the analog watchdog interrupt. In Scan mode if the watchdog thresholds are crossed, scan is Bit 6 aborted only if this bit is enabled. 0: Analog Watchdog interrupt disabled 1: Analog Watchdog interrupt enabled 473/519 www.BDTIC.com/ST...
  • Page 474 This bit is set by software to start conversion and cleared by hardware as soon as conversion starts. It starts a conversion of a a group of regular channels if Bit 22 SWSTART is selected as trigger event by the EXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of regular channels 474/519 www.BDTIC.com/ST...
  • Page 475 110: External interrupt 15 111: JSWSTART ALIGN: Data Alignment This bit is set and cleared by software. Refer to Figure 171.and Figure 172. Bit 11 0: Right Alignment 1: Left Alignment Bits 10:9 Reserved, must be kept cleared. 475/519 www.BDTIC.com/ST...
  • Page 476 0: Disable ADC conversion/calibration and go to power down mode. 1: Enable ADC and to start conversion Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is not triggered. This is to prevent triggering an erroneous conversion. 476/519 www.BDTIC.com/ST...
  • Page 477 These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles Bits 26:0 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 477/519 www.BDTIC.com/ST...
  • Page 478 These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles Bits 29:0 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 478/519 www.BDTIC.com/ST...
  • Page 479 Address offset: 24h Reset value: 0000 0000h Reserved Reserved HT[11:0] Bits 31:12 Reserved, must be kept cleared. HT[11:0] Analog watchdog high threshold Bits 11:0 These bits are written by software to define the high threshold for the Analog Watchdog. 479/519 www.BDTIC.com/ST...
  • Page 480 Address offset: 28h Reset value: 0000 0000h Reserved Reserved LT[11:0] Bits 31:12 Reserved, must be kept cleared. LT[11:0] Analog watchdog low threshold Bits 11:0 These bits are written by software to define the low threshold for the Analog Watchdog. 480/519 www.BDTIC.com/ST...
  • Page 481 These bits are written by software with the channel number (0..17) assigned as the 16th in the conversion sequence. Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence 481/519 www.BDTIC.com/ST...
  • Page 482 These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted. Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence 482/519 www.BDTIC.com/ST...
  • Page 483 7, 3, 3. (not 2, 7, 3) Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence 483/519 www.BDTIC.com/ST...
  • Page 484 – In ADC2: these bits are not used DATA[15:0]: Regular data These bits are read only. They contain the conversion result from the regular Bits 15:0 channels. The data is left or right-aligned as shown in Figure 171 Figure 172. 484/519 www.BDTIC.com/ST...

  • Page 485: Table 70. Adc - Register Map And Reset Values

    Reset Value ADC_SQR1 L[3:0] Regular channel sequence SQx_x bits Reserved Reset Value ADC_SQR2 Regular channel sequence SQx_x bits Reset Value ADC_SQR3 Regular channel sequence SQx_x bits Reset Value ADC_JSQR JL[1:0] Injected channel sequence JSQx_x bits Reserved Reset Value 485/519 www.BDTIC.com/ST...
  • Page 486 ADC_JDR1 JDATA[15:0] Reserved Reset Value ADC_JDR2 JDATA[15:0] Reserved Reset Value ADC_JDR3 JDATA[15:0] Reserved Reset Value ADC_JDR4 JDATA[15:0] Reserved Reset Value ADC_DR ADC2DATA[15:0] Regular DATA[15:0] Reset Value Refer to Table 1 on page 27 for the register boundary addresses. 486/519 www.BDTIC.com/ST...

  • Page 487: Figure 184. Block Diagram Of Stm32F10X-Level And Cortex-M3-Level Debug Support

    Trace Port TRACECK Bridge TPIU JTDO/ SWJ-DP TRACESWO AHB-AP TRACED[3:0] JNTRST Internal Private NVIC Peripheral Bus (PPB) JTCK/ SWCLK DBGMCU Note: The debug features embedded in the Cortex-M3 core are a subset of the ARM CoreSight Design Kit. 487/519 www.BDTIC.com/ST...
  • Page 488 CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2- pin) interface. The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP- AP port. The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port. 488/519 www.BDTIC.com/ST...
  • Page 489 SWCLK and SWDIO pins. This sequence is: Send more than 50 TCK cycles with TMS (SWDIO) =1 Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first) Send more than 50 TCK cycles with TMS (SWDIO) =1 489/519 www.BDTIC.com/ST...
  • Page 490 Purpose I/Os if using a small size for the debug port. The default state after reset is “000” (whole pins assigned for a full JTAG-DP connection). Only one of the 3 bits can be set (it is forbidden to set more than one bit). 490/519 www.BDTIC.com/ST...
  • Page 491 The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is no special recommendation for TCK. However, for STM32F10x, an integrated pull-down is used for JTCK. Having embedded pull-ups and pull-downs removes the need to add external resistors. 491/519 www.BDTIC.com/ST...
  • Page 492 For each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in the data scan chain. Note: Important: Once Serial-Wire is selected using the dedicated ARM JTAG sequence, the TMC TAP is automatically disabled (JTMS forced high). 492/519 www.BDTIC.com/ST...

  • Page 493: Figure 185. Jtag Tap Connections

    20.6.1 MCU device ID code The MCU STM32F10x integrates an MCU ID code. This ID identifies the ST MCU part- number and the die revision. It is part of the DBG_MCU Component and is mapped on the external PPB bus (see Section 20.15 on page...

  • Page 494: Table 71. Jtag Debug Port Data Registers

    Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read request Bits 2:0 = ACK[2:0] = 3-bit Acknowledge: 010 = OK/FAULT 001 = WAIT OTHER = reserved Refer to Table 72 for a description of the A(3:2) bits 494/519 www.BDTIC.com/ST...

  • Page 495: Table 72. 32-Bit Debug Port Registers Addressed Through The Shifted Value A[3:2]

    – Bits 7:4: APBANKSEL: select the active 4-words register window on the current AP – Bits 3:0: reserved DP RDBUFF register: Used to allow the debugger to get the final result after a sequence of operations (without requesting new JTAG-DP operation) 495/519 www.BDTIC.com/ST...

  • Page 496: Table 73. Packet Request (8-Bits)

    Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers. The packet request is always followed by the turnaround time (default 1 bit) where neither the host nor target drive the line. 496/519 www.BDTIC.com/ST...

  • Page 497: Table 74. Ack Response (3 Bits)

    The SW-DP implements a write buffer (for both DP or AP writes), that enables it to accept a write operation even when other transactions are still outstanding. If the write buffer is full, the target acknowledge response is “WAIT”. With the exception of 497/519 www.BDTIC.com/ST...

  • Page 498: Table 76. Sw-Dp Registers

    SW-DP registers CTRLSEL bit of A(3:2) Register Notes SELECT register The manufacturer code is not set to ST Read IDCODE code. 0x1BA01477 (identifies the SW-DP) Write ABORT Purpose is to: – request a system or debug power-up – configure the transfer operation for AP...
  • Page 499 Core debug is accessed through the core debug registers. Debug access to these registers is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can access these registers directly over the internal Private Peripheral Bus (PPB). 499/519 www.BDTIC.com/ST...
  • Page 500 In addition, it is possible to program any debug features under System Reset. Note: It is highly recommended for the debugger host to connect (set a breakpoint in the reset vector) under system reset. 500/519 www.BDTIC.com/ST...
  • Page 501 Hardware trace. The DWT generates these packets, and the ITM emits them. Time stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex-M3 clock or the bit clock rate of the Serial Wire Viewer (SWV) output clocks the counter. 501/519 www.BDTIC.com/ST...

  • Page 502: Table 77. Main Itm Registers

    Bit 2 = SYNCENA: this bit must be to 1 to enable the DWT to generate synchronization triggers so that the TPIU can then emit the synchronization packets. Bit 1 = TSENA (Timestamp Enable) Bit 0 = ITMENA: Global Enable Bit of the ITM 502/519 www.BDTIC.com/ST...
  • Page 503 The core does not allow FCLK or HCLK to be turned off during a debug session. As these are required for the debugger connection, during a debug, they must remain active. The MCU integrates special means to allow the user to debug software in low-power modes. 503/519 www.BDTIC.com/ST...
  • Page 504 POR Reset: 0x00000000 (not reset by system reset) Reserved DBG_ DBG_ DBG_ DBG_ DBG_ DBG_ DBG_ TRACE_ TRACE DBG_ WWDG DBG_ DBG_ Res. CAN_ TIM4_ TIM3_ TIM2_ TIM1_ IWDG MODE Reserved STAND STOP SLEEP STOP STOP STOP STOP STOP STOP [1:0] IOEN STOP 504/519 www.BDTIC.com/ST...
  • Page 505 1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU generate a system reset during STANDBY mode so that exiting from STANDBY is identical than fetching from reset 505/519 www.BDTIC.com/ST...
  • Page 506 The core embeds a simple TPIU, especially designed for low-cost debug (consisting of a special version of the CoreSight TPIU). The TPIU only supports ITM debug trace which is a limited trace as it only outputs information coming from the ITM. 506/519 www.BDTIC.com/ST...
  • Page 507 UM0306 Debug support (DBG) TRACECLKIN Domain CLK Domain TPIU TRACECLKIN TRACECK Asynchronous Trace Out TPIU Formatter TRACEDATA FIFO (serializer) [3:0] TRACESWO External PPB Bus 507/519 www.BDTIC.com/ST...
  • Page 508 TRACE_MODE[1:0] of the Debug MCU configuration Register (DBGMCU_CR). By default the TRACE pins are not assigned. This register is mapped on the external PPB and is reset by the PORESET (and not by the SYSTEM reset). It can be written by the debugger under SYSTEM reset. 508/519 www.BDTIC.com/ST...
  • Page 509 – if the corresponding byte was a data, this bit gives bit0 of the data. – if the corresponding byte was an ID change, this bit indicates when that ID change takes effect. 509/519 www.BDTIC.com/ST...
  • Page 510 If the bit SYNENA of the ITM is set, then the ITM synchronization packets will follow (0x80_00_00_00_00_00), formatted by the TPUI (trace source ID added). 20.16.6 Synchronous mode The trace data output size can be configured to 4, 2 or 1 pin: TRACED(3:0) The output clock is output to the debugger (TRACECK) 510/519 www.BDTIC.com/ST...
  • Page 511 The TPIU APB registers can be read and written only if the bit TRCENA of the Debug Exception and Monitor Control Register (DEMCR) is set. Otherwise, the registers are read as zero (the output of this bit enables the PCLK of the TPIU). 511/519 www.BDTIC.com/ST...

  • Page 512: Table 78. Important Tpiu Registers

    Write the DBGMCU Control Register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os for async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F) Configure the ITM and write the ITM Stimulus register to output a value 512/519 www.BDTIC.com/ST...

  • Page 513: Table 79. Dbg - Register Map And Reset Values

    UM0306 Debug support (DBG) 20.17 DBG register map The following table summarizes the Debug registers. Table 79. DBG - register map and reset values Addr. Register DBGMCU_ DEV_ID IDCODE Reserved Reset Value DBGMCU_CR Reserved Reset Value 513/519 www.BDTIC.com/ST...

  • Page 514: Table 80. Document Revision History

    Revision history UM0306 Revision history Table 80. Document revision history Date Revision Changes 01-Jun-2007 Initial release. 514/514 www.BDTIC.com/ST...
  • Page 515 CAN_RF1R ......309 CAN_RIxR ......317 515/519 www.BDTIC.com/ST...
  • Page 516 IWDG_RLR ......142 IWDG_SR ......142 516/519 www.BDTIC.com/ST...
  • Page 517 TIM1_CR2 ......193 TIM1_DCR ......218 517/519 www.BDTIC.com/ST...
  • Page 518 WWDG_CR ......148 WWDG_SR ......149 518/519 www.BDTIC.com/ST...
  • Page 519 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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