ST STM32F405 Reference Manual page 924

Serial peripheral interface (SPI)
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I
mode.
This bit is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 28.4.4: Clock
Note: This bit should be configured when the I
mode.
Bits 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to
Note: These bits should be configured when the I
master mode.
924/1749
generator. Not used in SPI mode.
Section 28.4.4: Clock generator. Not used in SPI mode.
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
2
S is disabled. It is used only when the I
RM0090 Rev 18
RM0090
2
S is in master
2
S is in master
2
S is in