Figure 16. Clock Tree - ST STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
OSC32_IN
LSE OSC
32.768 kHz
OSC32_OUT
MCO2
/1 to 5
MCO1
/1 to 5
OSC_OUT
4-26 MHz
HSE OSC
OSC_IN
VCO
xN
PLL
VCO
xN
PLLI2S
I2S_CKIN
VCO
xN
PLLSAI
ETH_MII_TX_CLK_MII
PHY Ethernet
25 to 50 MHz
ETH_MII_RX_CLK_MI
I
USB2.0 PHY OTG_HS_ULPI_CK
24 to 60 MHz
1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
2. When TIMPRE bit of the RCC_DCKCFGR register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, otherwise
TIMxCLK = 2x PCLKx.
3. When TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise
TIMxCLK = 4x PCLKx.
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Figure 16. Clock tree

Watchdog
LSI
enable
LSI RC
32 kHz
RTCSEL[1:0]
LSE
SYSCLK
LSE
/2 to 31
HSI
16 MHz
HSI RC
PLLCLK
HSE
/M
/P
PLL48CK
/Q
/R
/P
/Q
PLLI2SCLK
/R
Ext. clock
PLLSAICLK
DIV
/P
PLLSAICLK
DIV
/Q
PLLLCDCLK
/R
DIV
Peripheral
clock enable
/2,20
Peripheral
clock enable
Peripheral
clock enable
IWDGCLK
To Independent
watchdog
RTC
RTCCLK
enable to RTC
HSE_RTC
Peripheral
clock enable
180 MHz max.
Clock
enable
/8
SW
HSI
HSE
AHB
PRESC
/1,2,..512
SYSCLK
180 MHz
APBx
max
PRESC
/1,2,4,8,16
if (APBx presc =
1x1 else x2
Peripheral
clock enable
I2SSRC
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
MACTXCLK
MII_RMII_SEL in SYSCFG_PMC to Ethernet MAC
MACRXCLK
MACRMIICLK
Peripheral
clock enable
RM0090 Rev 18
Ethernet
PTP clock
HCLK
to AHB bus, core,
memory and DMA
to Cortex System timer
FCLK Cortex
free-running clock
Peripheral clock
enable
APBx peripheral clocks
Peripheral clock
enable
APBx timer clocks
48 MHz
clocks
I2S clocks
SAI1_A clock
SAI1_B clock
LCD-TFT
clock
USBHS
ULPI clock
RM0090
MS30434V2