Memory And Bus Architecture; System Architecture - ST STM32F405 Reference Manual

RM0090
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Memory and bus architecture

2.1

System architecture

In STM32F405xx/07xx and STM32F415xx/17xx, the main system consists of 32-bit
multilayer AHB bus matrix that interconnects:
The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
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Eight masters:
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Seven slaves:
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The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. The 64-
Kbyte CCM (core coupled memory) data RAM is not part of the bus matrix and can be
accessed only through the CPU. This architecture is shown in
®
Cortex -M4 with FPU core I-bus, D-bus and S-bus
DMA1 memory bus
DMA2 memory bus
DMA2 peripheral bus
Ethernet DMA bus
USB OTG HS DMA bus
Internal Flash memory ICode bus
Internal Flash memory DCode bus
Main internal SRAM1 (112 KB)
Auxiliary internal SRAM2 (16 KB)
AHB1 peripherals including AHB to APB bridges and APB peripherals
AHB2 peripherals
FSMC
RM0090 Rev 18
Memory and bus architecture
Figure 1.
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