Flash Control Register (Flash_Cr) For; Stm32F42Xxx And Stm32F43Xxx - ST STM32F405 Reference Manual

RM0090
3.9.8

Flash control register (FLASH_CR) for

STM32F42xxx and STM32F43xxx

The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31 30 29 28
LOCK
Reserved
rs
15 14 13 12
MER1
Reserved
rw
Bit 31 LOCK: Lock
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 30:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is set
to 1.
Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to
1.
Bits 23:17 Reserved, must be kept cleared.
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bit 15 MER1: Mass Erase of bank 2 sectors
Erase activated for bank 2 user sectors 12 to 23.
Bits 14:10 Reserved, must be kept cleared.
Bits 9:8 PSIZE[1:0]: Program size
These bits select the program parallelism.
27 26 25
ERRIE
rw
11 10 9
PSIZE[1:0]
rw
0: Error interrupt generation disabled
1: Error interrupt generation enabled
0: Interrupt generation disabled
1: Interrupt generation enabled
00 program x8
01 program x16
10 program x32
11 program x64
24 23 22
EOPIE
rw
8 7 6
SNB[4:0]
rw rw rw
RM0090 Rev 18
Embedded Flash memory interface
21 20 19 18
Reserved
5 4 3 2
MER
rw rw rw rw
17 16
STRT
rs
1 0
SER PG
rw rw
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