ST STM32F405 Reference Manual page 70

Memory and bus architecture
The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It
is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot
mode.
BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been
sampled, the corresponding GPIO pin is free and can be used for other purposes.
The BOOT pins are also resampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode. After this startup delay is over, the CPU fetches the top-of-stack value from address
0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.
Note: When the device boots from SRAM, in the application initialization code, you have to
relocate the vector table in SRAM using the NVIC exception table and the offset register.
In STM32F42xxx and STM32F43xxx devices, when booting from the main Flash memory,
the application software can either boot from bank 1 or from bank 2. By default, boot from
bank 1 is selected.
To select boot from Flash memory bank 2, set the BFB2 bit in the user option bytes. When
this bit is set and the boot pins are in the boot from main Flash memory configuration, the
device boots from system memory, and the boot loader jumps to execute the user
application programmed in Flash memory bank 2. For further details, please refer to
AN2606.
Embedded bootloader
The embedded bootloader mode is used to reprogram the Flash memory using one of the
following serial interfaces:
•
USART1 (PA9/PA10)
•
USART3 (PB10/11 and PC10/11)
•
CAN2 (PB5/13)
•
USB OTG FS (PA11/12) in Device mode (DFU: device firmware upgrade).
The USART peripherals operate at the internal 16 MHz oscillator (HSI) frequency, while the
CAN and USB OTG FS require an external clock (HSE) multiple of 1 MHz (ranging from 4 to
26 MHz).
The embedded bootloader code is located in system memory. It is programmed by ST
during production. For additional information, refer to application note AN2606.
Physical remap in STM32F405xx/07xx and STM32F415xx/17xx
Once the boot pins are selected, the application software can modify the memory
accessible in the code area (in this way the code can be executed through the ICode bus in
place of the System bus). This modification is performed by programming the
SYSCFG memory remap register (SYSCFG_MEMRMP)
The following memories can thus be remapped:
•
Main Flash memory
• System memory
•
Embedded SRAM1 (112 KB)
• FSMC bank 1 (NOR/PSRAM 1 and 2)
70/1749 RM0090 Rev 18
Section 9.2.1:
in the SYSCFG controller.
RM0090