ST STM32F405 Reference Manual page 171

RM0090
Bit 25 ETHMACRST: Ethernet MAC reset
Bit 24 Reserved, must be kept at reset value.
Bit 23 DMA2DRST: DMA2D reset
Bit 22 DMA2RST: DMA2 reset
Bit 21 DMA1RST: DMA2 reset
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Bit 11 Reserved, must be kept at reset value.
Bit 10 GPIOKRST: IO port K reset
Bit 9 GPIOJRST: IO port J reset
Bit 8 GPIOIRST: IO port I reset
Bit 7 GPIOHRST: IO port H reset
Bit 6 GPIOGRST: IO port G reset
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
This bit is set and cleared by software.
0: does not reset Ethernet MAC
1: resets Ethernet MAC
This bit is set and reset by software.
0: does not reset DMA2D
1: resets DMA2D
This bit is set and cleared by software.
0: does not reset DMA2
1: resets DMA2
This bit is set and cleared by software.
0: does not reset DMA2
1: resets DMA2
This bit is set and cleared by software.
0: does not reset CRC
1: resets CRC
This bit is set and cleared by software.
0: does not reset IO port K
1: resets IO port K
This bit is set and cleared by software.
0: does not reset IO port J
1: resets IO port J
This bit is set and cleared by software.
0: does not reset IO port I
1: resets IO port I
This bit is set and cleared by software.
0: does not reset IO port H
1: resets IO port H
This bit is set and cleared by software.
0: does not reset IO port G
1: resets IO port G
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