Figure 158. Control Circuit In External Clock Mode 2; Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32F405 Reference Manual

Hide thumbs Also See for STM32F405:

Table of Contents

The delay between the rising edge on ETR and the actual clock of the counter is due to the

resynchronization circuit on the ETRP signal.

Counter clock = CK_INT =CK_PSC

Capture/compare channels

Each Capture/Compare channel (see

(including a shadow register), an input stage for capture (with digital filter, multiplexing and

prescaler) and an output stage (with comparator and output control).

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be

used as trigger input by the slave mode controller or as the capture command. It is

prescaled before the capture register (ICxPS).

The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

Figure 158. Control circuit in external clock mode 2

Counter register

General-purpose timers (TIM2 to TIM5)

159) is built around a capture/compare register

TI1F_Falling

(from channel 2)

TI2F_falling

(from channel 2)

RM0090 Rev 18

to the slave mode controller

/1, /2, /4, /8

(from slave mode

Table of Contents