ST STM32F405 Reference Manual page 416

Analog-to-digital converter (ADC)
13.13.2 ADC control register 1 (ADC_CR1)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Reserved
15 14 13 12
JDISCE
DISCNUM[2:0]
N
rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 OVRIE: Overrun interrupt enable
Bits 25:24 RES[1:0]: Resolution
Bit 23 AWDEN: Analog watchdog enable on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
Bits 21:16 Reserved, must be kept at reset value.
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count
Bit 12 JDISCEN: Discontinuous mode on injected channels
416/1749
27 26 25
OVRIE RES
rw rw
11 10 9
DISC AWDSG
JAUTO
EN L
rw rw rw
This bit is set and cleared by software to enable/disable the Overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
These bits are written by software to select the resolution of the conversion.
00: 12-bit (15 ADCCLK cycles)
01: 10-bit (13 ADCCLK cycles)
10: 8-bit (11 ADCCLK cycles)
11: 6-bit (9 ADCCLK cycles)
This bit is set and cleared by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
This bit is set and cleared by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
These bits are written by software to define the number of regular channels to be converted
in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
24 23 22
AWDEN JAWDEN
rw rw rw
8 7 6
SCAN JEOCIE AWDIE
rw rw rw
RM0090 Rev 18
21 20 19 18
Reserved
5 4 3 2
EOCIE AWDCH[4:0]
rw rw rw rw
RM0090
17 16
1 0
rw rw