Pwr Power Control/Status Register (Pwr_Csr); For Stm32F42Xxx And Stm32F43Xxx - ST STM32F405 Reference Manual

RM0090
5.5.2

PWR power control/status register (PWR_CSR)

for STM32F42xxx and STM32F43xxx

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29 28
15 14 13 12
VOS
RDY
Res
r
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 UDRDY[1:0]: Under-drive ready flag
Bit 17 ODSWRDY: Over-drive mode switching ready
Bit 16 ODRDY: Over-drive mode ready
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BRE: Backup regulator enable
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
27 26 25
Reserved
11 10 9
BRE
Reserved
rw
These bits are set by hardware when MCU entered stop Under-drive mode and exited.
When the under-drive mode is enabled, these bits are not set as long as the MCU has not
entered stop mode yet. They are cleared by programming them to 1.
00: Under-drive is disabled
01: Reserved
10: Reserved
11:Under-drive mode is activated in Stop mode.
0: Over-drive mode is not active.
1: Over-drive mode is active on digital area on 1.2 V domain
0: Over-drive mode not ready.
1: Over-drive mode ready
0: Not ready
1: Ready
When set, the Backup regulator (used to maintain backup SRAM content in Standby and
V modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup
BAT
SRAM can still be used but its content will be lost in the Standby and V
the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
the data written into the RAM will be maintained in the Standby and V
0: Backup regulator disabled
1: Backup regulator enabled
or by a power reset.
24 23 22
8 7 6
EWUP
Reserved.
rw
RM0090 Rev 18
Power controller (PWR)
21 20 19 18
UDRDY[1:0]
rc_w1 rc_w1
5 4 3 2
BRR PVDO
r r
modes. Once set,
BAT
modes.
BAT
17 16
ODSWRDY ODRDY
r r
1 0
SBF WUF
r r
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