Figure 45. Timing Diagram - ST STM32F405 Reference Manual

Analog-to-digital converter (ADC)
13.3.5 Continuous conversion mode
In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one.
This mode is started with the CONT bit at 1 either by external trigger or by setting the
SWSTRT bit in the ADC_CR2 register (for regular channels only).
After each conversion:
•
If a regular group of channels was converted:
–
–
–
Note: Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to
13.3.6 Timing diagram
As shown in
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
ADC_CLK
ADON
SWSTART/
JSWSTART
ADC
EOC
13.3.7 Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 66
watchdog on one or more channels.
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The last converted data are stored into the 16-bit ADC_DR register
The EOC (end of conversion) flag is set
An interrupt is generated if the EOCIE bit is set
Figure 45, the ADC needs a stabilization time of t

Figure 45. Timing diagram

Start 1st conversion
ADC conversion
Conversion time
t STAB
(total conv. time)
shows how the ADC_CR1 register should be configured to enable the analog
Auto-injection section)
Software clears the EOC bit
RM0090 Rev 18
.
before it starts
STAB
Start next conversion
Next ADC conversion
RM0090
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