ST STM32F405 Reference Manual page 356

Chrom-Art Accelerator™ controller (DMA2D)
11.5.4 DMA2D foreground memory address register (DMA2D_FGMAR)
Address offset: 0x000C
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 MA[31: 0]: Memory address
11.5.5 DMA2D foreground offset register (DMA2D_FGOR)
Address offset: 0x0010
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
rw rw
Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line offset
356/1749
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
Address of the data used for the foreground image. This register can only be written
when data transfers are disabled. Once the data transfer has started, this register is
read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-
bit per pixel format must be 8-bit aligned.
27 26 25 24
11 10 9 8
rw rw rw rw
Line offset used for the foreground expressed in pixel. This value is used to generate
the address. It is added at the end of each line to determine the starting address of the
next line.
These bits can only be written when data transfers are disabled. Once a data transfer
has started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.
RM0090 Rev 18
23 22 21
MA[31:16]
rw rw rw
7 6 5
MA[15:0]
rw rw rw
23 22 21
Reserved
7 6 5
LO[13:0]
rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
20 19 18 17
4 3 2 1
rw rw rw rw
RM0090
16
rw
0
rw
16
0
rw