Figure 21. Clock Tree - ST STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
OSC32_IN
LSE OS C
32.768 kHz
OSC32_OUT
MCO2
/1 to 5
MCO1
/1 to 5
OSC _OUT
4-26 MHz
HS E O S C
OS C _IN
VCO
xN
PLL
VCO
xN
PLLI2S
I2S_CKIN
ETH_MII_TX_CLK_MII
PHY Ethernet
25 to 50 MHz
ETH_MII_RX_
CLK_MII
OTG_HS_ULPI_CK
USB2.0 PHY
24 to 60 MHz
1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
216/1749

Figure 21. Clock tree

LSI
LSI RC
32 kHz
SYSCLK
LSE
/2 to 31
16 MHz
HSI
HS I R C
HSE
/ M
/ P
PLL48CK
/ Q
/ R
/ P
I2SSRC
/ Q
PLLI2SCLK
/ R
Ext. clock
Peripheral
clock enable
MII_RMII_SEL in SYSCFG_PMC
/2,20
Peripheral
clock enable
Peripheral
clock enable
RM0090 Rev 18
Watchdog
IWDGCLK
enable
RTC S E L[1:0]
RTC
RTCCLK
enable
LSE
HSE_RTC
SW
HSI
HSE
AHB
PRESC
PLLCLK / 1,2,..512
SYSCLK
168 MHz
max
/ 1,2,4,8,16
MACTXCLK
to Ethernet MAC
MACRXCLK
MACRMIICLK
to independent
watchdog
to RTC
Peripheral
Ethernet
clock enable
PTP clock
HCLK
168 MHz max.
to AHB bus, core,
Clock
memory and DMA
Enable
to Cortex System
/8
timer
FCLK Cortex
free-running clock
Peripheral
APBx
clock enable
PRESC
Peripheral
clock enable
if (APBx presc = 1x1
else x2
Peripheral
clock enable
Peripheral
I2S clocks
clock enable
Peripheral
clock enable
ULPI clock
RM0090
APBx
peripheral
clocks
APBx timer
clocks
48 MHz
clocks
USBHS
ai16088d