Figure 267. Receiving 0X8Eaa33; Figure 268. I; Figure 269. Example - ST STM32F405 Reference Manual

RM0090

Figure 268. I

When 16-bit data frame extended to 32-bit channel frame is selected during the I
configuration phase, only one access to SPI_DR is required. The 16 remaining bits are
forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the
operation shown in
For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its
interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes
place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first
16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents
underrun or overrun conditions (depending on the direction of the data transfer).
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.

Figure 267. Receiving 0x8EAA33

First read to Data register
0x8EAA
2
S Philips standard (16-bit extended to 32-bit packet frame with
CK
WS
Transmission
16-bit data
SD
MSB
Channel left 32-bit
Figure 269 is required.
RM0090 Rev 18
Second read to Data register
0x33XX
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything
CPOL = 0)
Reception
16-bit remaining 0 forced
LSB

Figure 269. Example

Only one access to SPIx_DR
0x76A3
Serial peripheral interface (SPI)
Channel right
MS19594V1
MS19599V1
2
S
MS19595V1
903/1749
925