Figure 216. Block Diagram (Stm32F415/417Xx) - ST STM32F405 Reference Manual

Cryptographic processor (CRYP)
23.3 CRYP functional description
The cryptographic processor implements a Triple-DES (TDES, that also supports DES) core
and an AES cryptographic core.
cores.
Since the TDES and the AES algorithms use block ciphers, incomplete input data blocks
have to be padded prior to encryption (extra bits should be appended to the trailing end of
the data string). After decryption, the padding has to be discarded. The hardware does not
manage the padding operation, the software has to handle it.
Figure 216
722/1749
Section 23.3.1
shows the block diagram of the cryptographic processor.

Figure 216. Block diagram (STM32F415/417xx)

Status
CRYP_SR
DMA control register
CRYP_DMACR
Interrupt registers
CRYP_IMSCR
CRYP_RIS
CRYP_MISR
Control register
CRYP_CR
Initialization vectors
IV0...IV127
CRYP_IV0...IV1
Key
CRYP_K0. ..K3
RM0090 Rev 18
and Section 23.3.2
32-bit AHB2 bus
CRYP_DIN
8 × 32-bit
IN FIFO
swappi ng
k255...k0
provide details on these
CRYP_DOUT
8 × 32-bit
OUT FIFO
swappin g
DES/TDES/AES
Processor core
RM0090
ai16068b