Embedded Flash Memory Interface; Introduction; Main Features; Figure 3. Flash Memory Interface Connection Inside System Architecture (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx) - ST STM32F405 Reference Manual

RM0090
3

Embedded Flash memory interface

3.1

Introduction

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2

Main features

•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
Prefetch on I-Code
•
64 cache lines of 128 bits on I-Code
•
8 cache lines of 128 bits on D-Code
Figure 3
Figure 3. Flash memory interface connection inside system architecture
Cortex
core
shows the Flash memory interface connection inside the system architecture.
(STM32F405xx/07xx and STM32F415xx/17xx)
Cortex-M4 with FPU
I-Code bus
D-code bus
CCM data
RAM
DMA1
DMA2
USB HS
Ethernet
Access to instruction in Flash memory
Access to data and literal pool in Flash memory
FLITF register access
AHB
32-bit
instruction
I-Code
bus
D-Code
AHB
S bus
32-bit
data bus
AHB
32-bit
system bus
RM0090 Rev 18
Embedded Flash memory interface
Flash
memory
Flash interface
bus
128 bits
FLITF registers
Flash
memory
AHB
periph1
SRAM and
External
memories
AHB
periph2
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