ST STM32F405 Reference Manual page 867

RM0090
Bit 8 BERR: Bus error
– Set by hardware when the interface detects an SDA rising or falling edge while SCL is high,
– Cleared by software writing 0, or by hardware when PE=0.
Bit 7 TxE: Data register empty (transmitters)
– Set when DR is empty in transmission. TxE is not set during address phase.
– Cleared by software writing to the DR register or by hardware after a start or a stop condition
Note: TxE is not cleared by writing the first data being transmitted, or by writing data when
Bit 6 RxNE: Data register not empty (receivers)
– Set when data register is not empty in receiver mode. RxNE is not set during address phase.
– Cleared by software reading or writing the DR register or by hardware when PE=0.
Note: RxNE is not cleared by reading data when BTF is set, as the data register is still full.
Bit 5 Reserved, must be kept at reset value
Bit 4 STOPF: Stop detection (slave mode)
– Set by hardware when a Stop condition is detected on the bus by the slave after an
– Cleared by software reading the SR1 register followed by a write in the CR1 register, or by
Note: The STOPF bit is not set after a NACK reception.
Bit 3 ADD10: 10-bit header sent (Master mode)
– Set by hardware when the master has sent the first byte in 10-bit address mode.
– Cleared by software reading the SR1 register followed by a write in the DR register of the
Note: ADD10 bit is not set after a NACK reception
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
occurring in a non-valid position during a byte transfer.
0: Data register not empty
1: Data register empty
or when PE=0.
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)
BTF is set, as in both cases the data register is still empty.
0: Data register empty
1: Data register not empty
RxNE is not set in case of ARLO event.
0: No Stop condition detected
1: Stop condition detected
acknowledge (if ACK=1).
hardware when PE=0
It is recommended to perform the complete clearing sequence (READ SR1 then
WRITE CR1) after the STOPF is set. Refer to
0: No ADD10 event occurred.
1: Master has sent first address byte (header).
second address byte, or by hardware when PE=0.
Inter-integrated circuit (I2C) interface
RM0090 Rev 18
Figure 242.
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