ST STM32F405 Reference Manual page 562

Advanced-control timers (TIM1 and TIM8)
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
17.4.2 TIM1 and TIM8 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
15 14 13
OIS4 OIS3N OIS3
Res.
rw rw
Bit 15 Reserved, must be kept at reset value.
Bit 14 OIS4: Output Idle state 4 (OC4 output)
Bit 13 OIS3N: Output Idle state 3 (OC3N output)
Bit 12 OIS3: Output Idle state 3 (OC3 output)
Bit 11 OIS2N: Output Idle state 2 (OC2N output)
Bit 10 OIS2: Output Idle state 2 (OC2 output)
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This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
12 11 10 9
OIS2N OIS2 OIS1N
rw rw rw rw
refer to OIS1 bit
refer to OIS1N bit
refer to OIS1 bit
refer to OIS1N bit
refer to OIS1 bit
8 7 6
OIS1 TI1S MMS[2:0]
rw rw rw
RM0090 Rev 18
5 4 3 2
CCDS CCUS
rw rw rw rw
RM0090
1 0
CCPC
Res.
rw