ST STM32F405 Reference Manual page 644

General-purpose timers (TIM2 to TIM5)
Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5).
Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
18.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
Address offset: 0x3C
Reset value: 0x0000 0000
31 30 29
rw/ro rw/ro rw/ro rw/ro
15 14 13
rw/ro rw/ro rw/ro rw/ro
Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5).
Bits 15:0 CCR3[15:0]: Low Capture/Compare value
18.4.16 TIMx capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000 0000
31 30 29
rw/ro rw/ro rw/ro rw/ro
15 14 13
rw/ro rw/ro rw/ro rw/ro
644/1749
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.
28 27 26 25
CCR3[31:16] (depending on timers)
rw/ro rw/ro rw/ro
12 11 10 9
rw/ro rw/ro rw/ro
If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR register (bit
OC3PE). Else the preload value is copied in the active capture/compare 3 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC3 output.
If channel CC3 is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3). The
TIMx_CCR3 register is read-only and cannot be programmed.
28 27 26 25
CCR4[31:16] (depending on timers)
rw/ro rw/ro rw/ro
12 11 10 9
rw/ro rw/ro rw/ro
24 23 22
rw/ro rw/ro rw/ro
8 7 6
CCR3[15:0]
rw/ro rw/ro rw/ro
24 23 22
rw/ro rw/ro rw/ro
8 7 6
CCR4[15:0]
rw/ro rw/ro rw/ro
RM0090 Rev 18
21 20 19 18
rw/ro rw/ro rw/ro rw/ro
5 4 3 2
rw/ro rw/ro rw/ro rw/ro
21 20 19 18
rw/ro rw/ro rw/ro rw/ro
5 4 3 2
rw/ro rw/ro rw/ro rw/ro
RM0090
17 16
rw/ro rw/ro
1 0
rw/ro rw/ro
17 16
rw/ro rw/ro
1 0
rw/ro rw/ro