ST STM32F405 Reference Manual page 243

RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bit 21 DMA1EN: DMA1 clock enable
Bit 20 CCMDATARAMEN: CCM data RAM clock enable
Bit 19 Reserved, must be kept at reset value.
Bit 18 BKPSRAMEN: Backup SRAM interface clock enable
Bits 17:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 GPIOIEN: IO port I clock enable
Bit 7 GPIOHEN: IO port H clock enable
Bit 6 GPIOGEN: IO port G clock enable
Bit 5 GPIOFEN: IO port F clock enable
Bit 4 GPIOEEN: IO port E clock enable
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Set and cleared by software.
0: CCM data RAM clock disabled
1: CCM data RAM clock enabled
Set and cleared by software.
0: Backup SRAM interface clock disabled
1: Backup SRAM interface clock enabled
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Set and cleared by software.
0: IO port I clock disabled
1: IO port I clock enabled
Set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
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