Figure 190. Control Circuit In Normal Mode, Internal Clock Divided By 1 - ST STM32F405 Reference Manual

General-purpose timers (TIM9 to TIM14)
19.3.3 Clock selection
The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1 (for TIM9 and TIM12): external input pin (TIx)
•
Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from
another timer. Refer to
Internal clock source (CK_INT)
The internal clock source is the default clock source for TIM10/TIM11 and TIM13/TIM14.
For TIM9 and TIM12, the internal clock source is selected when the slave mode controller is
disabled (SMS='000'). The CEN bit in the TIMx_CR1 register and the UG bit in the
TIMx_EGR register are then used as control bits and can be changed only by software
(except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the
prescaler is clocked by the internal clock CK_INT.
Figure 190
without prescaler.

Figure 190. Control circuit in normal mode, internal clock divided by 1

CEN=CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
External clock source mode 1(
This mode is selected when SMS='111' in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.
658/1749
Using one timer as prescaler for another timer
shows the behavior of the control circuit and of the upcounter in normal mode,
Internal clock
UG
CNT_INIT
31
3 2 33 34 35 36
2
TIM9 and TIM1 )
RM0090 Rev 18
for more details.
00 01 02
03 04 05
RM0090
06 07
MS31085V2