Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
6.3.26
RCC register map
Table 33
Table 33. RCC register map and reset values for STM32F42xxx and STM32F43xxx
Addr.
Register
offset
name
0x00
RCC_CR
RCC_PLLCFG
0x04
Reserved
R
0x08
RCC_CFGR
0x0C
RCC_CIR
RCC_AHB1RS
0x10
TR
RCC_AHB2RS
0x14
TR
RCC_AHB3RS
0x18
TR
0x1C
Reserved
RCC_APB1RS
0x20
TR
RCC_APB2RS
0x24
TR
0x28
Reserved
0x2C
Reserved
RCC_
0x30
AHB1ENR
RCC_
0x34
AHB2ENR
RCC_
0x38
AHB3ENR
0x3C
Reserved
210/1749
gives the register map and reset values.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RM0090 Rev 18
RM0090
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