Table 103. Tim9/12 Register Map And Reset Values - ST STM32F405 Reference Manual

General-purpose timers (TIM9 to TIM14)
19.4.13 TIM9/12 register map
TIM9/12 registers are mapped as 16-bit addressable registers as described below. The
reserved memory areas are highlighted in gray in the table.
Offset Register
TIMx_CR1
0x00
Reset value
TIMx_SMCR
0x08
Reset value
TIMx_DIER
0x0C
Reset value
TIMx_SR
0x10
Reset value
TIMx_EGR
0x14
Reset value
TIMx_CCMR1
Output Compare
mode
Reset value
0x18
TIMx_CCMR1
Input Capture
mode
Reset value
0x1C
TIMx_CCER
0x20
Reset value
TIMx_CNT
0x24
Reset value
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value
0x30
TIMx_CCR1
0x34
Reset value
684/1749

Table 103. TIM9/12 register map and reset values

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RM0090 Rev 18
Reserved
Reserved
Reserved
OC2M
[2:0]
0 0
IC2F[3:0]
0 0 0
Reserved
Reserved
0 0 0
0 0 0
0 0 0
Reserved
0 0 0
CKD
[1:0]
Reserved
0 0 0
TS[2:0]
0 0 0
Reserved
0
Reserved
0 0 0
Reserved
0
CC2S OC1M
[1:0] [2:0]
0 0 0 0 0 0 0
IC2
CC2S
PSC IC1F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0
0 0
CNT[15:0]
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0
RM0090
0 0 0 0
SMS[2:0]
0 0 0 0
0 0 0
0 0 0
0 0 0
CC1
S
[1:0]
0 0 0 0 0
IC1 CC1
PSC S
[1:0] [1:0]
0 0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0