ST STM32F405 Reference Manual page 119

RM0090
When the backup domain is supplied by V
V is not present), the following functions are available:
DD
•
PC14 and PC15 can be used as LSE pins only
•
PC13 can be used as the RTC_AF1 pin (refer to
details about this pin configuration)
•
PI8 can be used as RTC_AF2
Backup domain access
After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is
protected against possible unwanted write accesses. To enable access to the backup
domain, proceed as follows:
•
Access to the RTC and RTC backup registers
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see
2. Set the DBP bit in the
STM32F42xxx and STM32F43xxx
3. Select the RTC clock source: see
4. Enable the RTC clock by programming the RTCEN [15] bit in the
Backup domain control register (RCC_BDCR)
•
Access to the backup SRAM
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see
STM32F415xx/17xx and STM32F42xxx and STM32F43xxx, respectively)
2. Set the DBP bit in the
and STM32F415xx/17xx
STM32F42xxx and STM32F43xxx
3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the
peripheral clock enable register
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to
Real-time clock
Backup SRAM
The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit
mode. Its content is retained even in Standby or V
regulator is enabled. It can be considered as an internal EEPROM when V
present.
When the backup domain is supplied by V
SRAM is powered from V
When the backup domain is supplied by V
V is not present), the backup SRAM is powered by a dedicated low-power regulator. This
DD
regulator can be ON or OFF depending whether the application needs the backup SRAM
function in Standby and V
Section 7.3.13 and
Section 5.4.1
Section 7.3.13 and
PWR power control register (PWR_CR) for STM32F405xx/07xx
and PWR power control register (PWR_CR) for
(RCC_AHB1ENR).
(RTC).
which replaces the V
DD
modes or not. The power-down of this regulator is controlled
BAT
RM0090 Rev 18
(analog switch connected to V
BAT
Table 37: RTC_AF1 pin
Section 6.3.13)
and PWR power control register (PWR_CR) for
to enable access to the backup domain
Section 7.2.8: RTC/AWU clock
Section 6.3.13 for STM32F405xx/07xx and
to enable access to the backup domain
mode when the low-power backup
BAT
(analog switch connected to V
DD
power supply to save battery life.
BAT
(analog switch connected to V
BAT
Power controller (PWR)
because
BAT
for more
Section 7.3.20: RCC
RCC AHB1
Section 26:
is always
BAT
), the backup
DD
because
BAT
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