Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr) - ST STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Bit 5 GPIOFEN: IO port F clock enable
Bit 4 GPIOEEN: IO port E clock enable
Bit 3 GPIODEN: IO port D clock enable
This bit is set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
Bit 1 GPIOBEN: IO port B clock enable
Bit 0 GPIOAEN: IO port A clock enable
6.3.11

RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Bit 6 RNGEN: Random number generator clock enable
182/1749
This bit is set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
This bit is set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
This bit is set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
This bit is set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
This bit is set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
28 27 26 25
12 11 10 9
Reserved
This bit is set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
This bit is set and cleared by software.
0: Random number generator clock disabled
1: Random number generator clock enabled
24 23 22
Reserved
8 7 6
OTGFS RNG HASH
EN EN
rw rw
RM0090 Rev 18
21 20 19 18
5 4 3 2
CRYP
EN EN
Reserved
rw rw
RM0090
17 16
1 0
DCMI
EN
rw