ST STM32F405 Reference Manual page 496

LCD-TFT controller (LTDC)
Bit 31 HSPOL: Horizontal Synchronization Polarity
Bit 30 VSPOL: Vertical Synchronization Polarity
Bit 29 DEPOL: Data Enable Polarity
Bit 28 PCPOL: Pixel Clock Polarity
Bits 27:17 Reserved, must be kept at reset value
Bit 16 DEN: Dither Enable
Bit 15 Reserved, must be kept at reset value
Bits 14:12 DRW[2:0]: Dither Red Width
Bit 11 Reserved, must be kept at reset value
Bits 10:8 DGW[2:0]: Dither Green Width
Bit 7 Reserved, must be kept at reset value
Bits 6:4 DBW[2:0]: Dither Blue Width
Bits 3:1 Reserved, must be kept at reset value
Bit 0 LTDCEN: LCD-TFT controller enable bit
496/1749
This bit is set and cleared by software.
0: Horizontal Synchronization polarity is active low
1: Horizontal Synchronization polarity is active high
This bit is set and cleared by software.
0: Vertical Synchronization is active low
1: Vertical Synchronization is active high
This bit is set and cleared by software.
0: Data Enable polarity is active low
1: Data Enable polarity is active high
This bit is set and cleared by software.
0: input pixel clock
1: inverted input pixel clock
This bit is set and cleared by software.
0: Dither disable
1: Dither enable
These bits return the Dither Red Bits
These bits return the Dither Green Bits
These bits return the Dither Blue Bits
This bit is set and cleared by software.
0: LTDC disable
1: LTDC enable
RM0090 Rev 18
RM0090