Figure 90. Counter Timing Diagram, Internal Clock Divided By 2; Figure 91. Counter Timing Diagram, Internal Clock Divided By 4; Figure 92. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F405 Reference Manual

RM0090

Figure 90. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 91. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 92. Counter timing diagram, internal clock divided by N

CK_PSC
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
RM0090 Rev 18
Advanced-control timers (TIM1 and TIM8)
0034 0035 0036
0035 0036
1F 20
0000 0001 0002 0003
0000 0001
00
MS31079V3
MS31080V3
MS31081V3
521/1749
588