ST STM32F405 Reference Manual page 370

Chrom-Art Accelerator™ controller (DMA2D)
Table 60. DMA2D register map and reset values (continued)
Offset Register
DMA2D_OOR
0x0040
Reset value
DMA2D_NLR
0x0044
Reset value
DMA2D_LWR
0x0048
Reset value
DMA2D_AMTCR
0x004C
Reset value
0x0050-
-
Ox03FF
DMA2D_FGCLUT
0x0400-
0x07FF
Reset value
DMA2D_BGCLUT
0x0800-
0x0BFF
Reset value
370/1749
Reserved
PL[13:0]
Res
0 0 0 0 0 0 0
Reserved
Reserved
APLHA[7:0][255:0]
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
APLHA[7:0][255:0]
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
0 0 0 0 0 0 0 0
0
0
Reserved
RED[7:0][255:0]
RED[7:0][255:0]
RM0090 Rev 18
LO[13:0]
0 0 0 0 0 0 0 0
NL[15:0]
0 0 0 0 0 0 0 0 0
LW[15:0]
0 0 0 0 0 0 0 0 0
DT[7:0]
0 0 0 0 0 0 0
GREEN[7:0][255:0]
GREEN[7:0][255:0]
RM0090
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
Reserved
0
BLUE[7:0][255:0]
BLUE[7:0][255:0]