Flash Option Control Register (Flash_Optcr) For; Stm32F405Xx/07Xx And Stm32F415Xx/17Xx - ST STM32F405 Reference Manual

Embedded Flash memory interface
Bits 7:3 SNB[3:0]: Sector number
These bits select the sector to erase.
Bit 2 MER: Mass Erase of bank 1 sectors
Erase activated of bank 1 sectors.
Bit 1 SER: Sector Erase
Sector Erase activated.
Bit 0 PG: Programming
Flash programming activated.
3.9.9

Flash option control register (FLASH_OPTCR) for

STM32F405xx/07xx and STM32F415xx/17xx

The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at
reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31 30 29
Reserved
15 14 13
rw rw rw
106/1749
0000: sector 0
0001: sector 1
...
01011: sector 11
01100: not allowed
01101: not allowed
01110: not allowed
01111: not allowed
10000: section 12
10001: section 13
...
11011 sector 23
11100: not allowed
11101: not allowed
11110: not allowed
11111: not allowed
28 27 26 25
rw rw rw
12 11 10 9
RDP[7:0]
rw rw rw rw
24 23 22
nWRP[11:0]
rw rw rw
8 7 6
nRST_ nRST_ WDG_
STDBY STOP SW
rw rw rw
RM0090 Rev 18
21 20 19 18
rw rw rw rw
5 4 3 2
BOR_LEV
Reserve
d
rw rw rw
RM0090
17 16
rw rw
1 0
OPTST OPTLO
RT CK
rs rs