Figure 152. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 153. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32F405 Reference Manual

RM0090

Figure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow)

Figure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
General-purpose timers (TIM2 to TIM5)
06 05 04 03 02
FD
FD
F7 F8 F9 FA FB FC
FD
FD
RM0090 Rev 18
01 00 01 02 03 04 05 06 07
36
36
36 35 34 33 32 31 30 2F
36
36
MS37360V1
MS37361V1
601/1749
649