ST STM32F405 Reference Manual page 344

Chrom-Art Accelerator™ controller (DMA2D)
The alpha channel can be:
•
kept as it is (no modification),
•
replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR,
•
or replaced by the original alpha value multiplied by the ALPHA[7:0] value of
DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.
AM[1:0]
00
01
10
11
11.3.5 DMA2D foreground and background CLUT interface
The CLUT interface manages the CLUT memory access and the automatic loading of the
CLUT.
Three kinds of accesses are possible:
•
CLUT read by the PFC during pixel format conversion operation
•
CLUT accessed through the AHB slave port when the CPU is reading or writing data
into the CLUT
•
CLUT written through the AHB master port when an automatic loading of the CLUT is
performed
The CLUT memory loading can be done in two different ways:
•
Automatic loading
The following sequence should be followed to load the CLUT:
a)
b)
c)
•
Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave
port to which the local CLUT memory is mapped.The foreground CLUT is located at
address offset 0x0400 and the background CLUT at address offset 0x0800.
The CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the
DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register
(background CLUT) as shown in
344/1749
Table 54. Alpha mode configuration
Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255
Program the CLUT address into the DMA2D_FGCMAR register (foreground
CLUT) or DMA2D_BGCMAR register (background CLUT)
Program the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register
(foreground CLUT) or DMA2D_BGPFCCR register (background CLUT).
Set the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or
DMA2D_BGPFCCR register (background CLUT) to start the transfer. During this
automatic loading process, the CLUT is not accessible by the CPU. If a conflict
occurs, a CLUT access error interrupt is raised assuming
DMA2D_CR.
Alpha mode
No modification
Replaced by value in DMA2D_xxPFCCR
Reserved
Table 55: Supported CLUT color
RM0090 Rev 18
RM0090
CAEIE is set to '1' in
mode.