Rcc Apb2 Peripheral Clock Enabled In Low Power Mode Register (Rcc_Apb2Lpenr) - ST STM32F405 Reference Manual

RM0090
6.3.19 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0x0477 7F33
Access: no wait state, word, half-word and byte access.
31 30 29 28
Reserved
15 14 13 12
SYSC
SPI4 SPI1
FG
Reser-
LPEN LPEN
LPEN
ved
rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 LTDCLPEN: LTDC clock enable during Sleep mode
Bits 25:23 Reserved, must be kept at reset value.
Bit 22 SAI1LPEN: SAI1 clock enable during Sleep mode
Bit 21 SPI6LPEN: SPI6 clock enable during Sleep mode
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
27 26 25
LTDC
LPEN
rw
11 10 9
SDIO ADC3 ADC2
LPEN LPEN LPEN
rw rw rw
This bit is set and cleared by software.
0: LTDC clock disabled during Sleep mode
1: LTDC clock enabled during Sleep mode
This bit is set and cleared by software.
0: SAI1 clock disabled during Sleep mode
1: SAI1 clock enabled during Sleep mode
This bit is set and cleared by software.
0: SPI6 clock disabled during Sleep mode
1: SPI6 clock enabled during Sleep mode
This bit is set and cleared by software.
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
This bit is set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
This bit is set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
24 23 22
SAI1 SPI6
LPEN LPEN
Reserved
rw
8 7 6
USART
ADC1
LPEN
Reserved
LPEN
rw
RM0090 Rev 18
21 20 19 18
SPI5 TIM11
Reser-
LPEN LPEN
ved
rw rw rw
5 4 3 2
USART
6 1
Reserved
LPEN
rw rw
17 16
TIM10 TIM9
LPEN LPEN
rw rw
1 0
TIM8 TIM1
LPEN LPEN
rw rw
197/1749
212