ST STM32F405 Reference Manual page 580

Advanced-control timers (TIM1 and TIM8)
17.4.10 TIM1 and TIM8 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15 14 13
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Bits 15:0 CNT[15:0]: Counter value
17.4.11 TIM1 and TIM8 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
17.4.12 TIM1 and TIM8 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
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Bits 15:0 ARR[15:0]: Auto-reload value
580/1749
12 11 10 9
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12 11 10 9
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The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in "reset mode").
12 11 10 9
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ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 17.3.1: Time-base unit
The counter is blocked while the auto-reload value is null.
8 7 6
CNT[15:0]
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8 7 6
PSC[15:0]
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8 7 6
ARR[15:0]
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for more details about ARR update and behavior.
RM0090 Rev 18
5 4 3 2
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5 4 3 2
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/ (PSC[15:0] + 1).
CK_PSC
5 4 3 2
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RM0090
1 0
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1 0
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1 0
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