Table 144. Usart Receiver's Tolerance When Div Fraction Is 0 - ST STM32F405 Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
Table 143. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
16. 9 MBps
17. 10.5 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
30.3.5 USART receiver tolerance to clock deviation
The USART asynchronous receiver works correctly only if the total clock system deviation is
smaller than the USART receiver's tolerance. The causes which contribute to the total
deviation are:
•
DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter's local oscillator)
• DQUANT: Error due to the baud rate quantization of the receiver
•
DREC: Deviation of the receiver's local oscillator
• DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
DTRA + DQUANT + DREC + DTCL < USART receiver's tolerance
The USART receiver's tolerance to properly receive data is equal to the maximum tolerated
deviation and depends on the following choices:
•
10- or 11-bit character length defined by the M bit in the USART_CR1 register
•
oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
•
use of fractional baud rate or not
•
use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register
M bit
0
1
988/1749
oversampling by 8
Oversampling by 8 (OVER8=1)
f = 42 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
N.A N.A
N.A N.A

Table 144. USART receiver's tolerance when DIV fraction is 0

OVER8 bit = 0
ONEBIT=0
3.75%
3.41%
PCLK
(1)(2)
(continued)
Value
programmed
in the baud
rate register
N.A
N.A
ONEBIT=1
4.375%
3.97%
RM0090 Rev 18
= 42 MHz or f
PCLK
f = 84 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
9.333 MBps 1.125
10.5 MBps 1
OVER8 bit = 1
ONEBIT=0
2.50%
2.27%
RM0090
= 84 MHz,
%
Error
3.7
0
ONEBIT=1
3.75%
3.41%