Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - ST STM32F405 Reference Manual

RM0090
6.3.14

RCC APB2 peripheral clock enable register (RCC_APB2ENR)

Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
Reserved
15 14 13
SPI1
SYSCF SPI4E
Reser-
G EN N
ved
rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 LTDCEN: LTDC clock enable
Bits 27: 23 Reserved, must be kept at reset value.
Bit 22 SAI1EN: SAI1 clock enable
Bit 21 SPI6EN: SPI6 clock enable
Bit 20 SPI5EN: SPI5 clock enable
Bit 18 TIM11EN: TIM11 clock enable
Bit 17 TIM10EN: TIM10 clock enable
Bit 16 TIM9EN: TIM9 clock enable
Bit 15 Reserved, must be kept at reset value.
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
28 27 26 25
LTDC
EN
rw
12 11 10 9
SDIO ADC3 ADC2
EN EN EN EN
rw rw rw rw
This bit is set and cleared by software.
0: LTDC clock disabled
1: LTDC clock enabled
This bit is set and cleared by software.
0: SAI1 clock disabled
1: SAI1 clock enabled
This bit is set and cleared by software.
0: SPI6 clock disabled
1: SPI6 clock enabled
This bit is set and cleared by software.
0: SPI5 clock disabled
1: SPI5 clock enabled
This bit is set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
This bit is set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
This bit is set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
24 23 22
SAI1EN SPI6EN SPI5EN
Reserved
rw
8 7 6
USART
ADC1
EN
Reserved
rw
RM0090 Rev 18
21 20 19 18
TIM11
EN
Res.
rw rw rw
5 4 3 2
USART
6 1
Reserved
EN EN
rw rw
17 16
TIM10 TIM9
EN EN
rw rw
1 0
TIM8 TIM1
EN EN
rw rw
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