ST STM32F405 Reference Manual page 201

RM0090
Bit 31 LPWRRSTF: Low-power reset flag
Bit 30 WWDGRSTF: Window watchdog reset flag
Bit 29 IWDGRSTF: Independent watchdog reset flag
Bit 28 SFTRSTF: Software reset flag
Bit 27 PORRSTF: POR/PDR reset flag
Bit 26 PINRSTF: PIN reset flag
Bit 25 BORRSTF: BOR reset flag
Bit 24 RMVF: Remove reset flag
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
This bit is set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
reset.
This bit is set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
This bit is set by hardware when an independent watchdog reset from V
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
This bit is set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
This bit is set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
This bit is set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Cleared by software by writing the RMVF bit.
This bit is set by hardware when a POR/PDR or BOR reset occurs.
0: No POR/PDR or BOR reset occurred
1: POR/PDR or BOR reset occurred
This bit is set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
RM0090 Rev 18
Low-power management
domain occurs.
DD
201/1749
212