Rcc Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr) - ST STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bit 2 TIM4EN: TIM4 clock enable
Bit 1 TIM3EN: TIM3 clock enable
Bit 0 TIM2EN: TIM2 clock enable
7.3.14

RCC APB2 peripheral clock enable register (RCC_APB2ENR)

Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
SPI1
SYSCF
Reser- Reser-
G EN
ved ved
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Bit 17 TIM10EN: TIM10 clock enable
Bit 16 TIM9EN: TIM9 clock enable
Bit 15 Reserved, must be kept at reset value.
248/1749
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
28 27 26 25
Reserved
12 11 10 9
SDIO ADC3 ADC2
EN EN EN EN
rw rw rw rw
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
24 23 22
8 7 6
USART
ADC1
EN
Reserved
rw
RM0090 Rev 18
21 20 19 18
TIM11
EN
rw
5 4 3 2
USART
6 1
Reserved
EN EN
rw rw
RM0090
17 16
TIM10 TIM9
EN EN
rw rw
1 0
TIM8 TIM1
EN EN
rw rw