Figure 114. Output Stage Of Capture/Compare Channel (Channel 1 To 3); Figure 115. Output Stage Of Capture/Compare Channel (Channel 4) - ST STM32F405 Reference Manual

RM0090

Figure 114. Output stage of capture/compare channel (channel 1 to 3)

ETRF
OC1REF
CNT>CCR1
Output
mode
CNT=CCR1
controller
(1)
OCxREF
OC5REF
OC1CE OC1M[3:0]
TIM1_CCMR1

Figure 115. Output stage of capture/compare channel (channel 4)

ETR
CNT>CCR4
CNT>CCR4
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
To the master mode
controller
OC1REFC
Output Dead-time
selector generator
DTG[7:0]
TIM1_BDTR
Output
mode
OC4REF
controller
OC1M[3:0]
TIM1_CCMR2
Advanced-control timers (TIM1 and TIM8)
'0'
x0
01
OC1_DT
11
OC1N_DT
11
10
'0'
0x
CC1NE CC1E
TIM1_CCER
To the master
mode controller
CC4P
TIM1_CCER
RM0090 Rev 18
0
Output
enable
1
circuit
CC1P
TIM1_CCER
0
Output
enable
1
circuit
CC1E TIM1_CCER
CC1NE
MOE OSSI
CC1NP
TIM1_CCER TIM1_BDTR
Output
0
OC4
enable
1
circuit
CC4E
TIM1_CCER
MOE OSSI
TIM1_BDTR
OIS4 TIM1_CR2
OC1
OC1N
OSSR
MS35909V1
MS37370V1
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