RM0090
Read CCR1H
S
read_in_progress
Read CCR1L
R
Input
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
CNT > CCR2
CNT = CCR2
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
19.3.5
Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
Figure 194. Capture/compare channel 1 main circuit
APB Bus
MCU-peripheral interface
8
Capture/compare preload register
capture_transfer
Capture /compare shadow register
Capture
Counter
Figure 195. Output stage of capture/compare channel (channel 1)
Output
OC1_REF
mode
controller
OC2M[2:0]
TIMx_CCMR1
RM0090 Rev 18
General-purpose timers (TIM9 to TIM14)
8
write_in_progress
Output
compare_transfer
mode
Comparator
CNT>CCR1
CNT=CCR1
To the master
mode controller
TIMx_CCER
write CCR1H
S
write CCR1L
R
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
TIMx_CCMR1
(from time
base unit)
0
Output
OC1
enable
1
circuit
CC1P
CC1E TIMx_CCER
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