ST STM32F405 Reference Manual page 875

RM0090
2
28.2.2 I S features
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Full duplex communication
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Half-duplex communication (only transmitter or receiver)
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Master or slave operations
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8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
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Data format may be 16-bit, 24-bit or 32-bit
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Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
• Programmable clock polarity (steady state)
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Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave), and Frame Error flag in reception and transmission mode (slave only)
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16-bit register for transmission and reception with one data register for both channel
sides
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Supported I
–
–
–
–
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Data direction is always MSB first
• DMA capability for transmission and reception (16-bit wide)
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Master clock may be output to drive an external audio component. Ratio is fixed at
256 × F
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Both I
accurate clock.
2
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I S (I2S2 and I2S3) clock can be derived from an external clock mapped on the
I2S_CKIN pin.
2
S protocols:
2
I S Phillps standard
MSB-justified standard (left-justified)
LSB-justified standard (right-justified)
PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
(where F is the audio sampling frequency)
S S
2
S (I2S2 and I2S3) have a dedicated PLL (PLLI2S) to generate an even more
RM0090 Rev 18
Serial peripheral interface (SPI)
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