Reset And Clock Control For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx(Rcc); Reset; System Reset - ST STM32F405 Reference Manual

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Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)

7 Reset and clock control for
STM32F405xx/07xx and STM32F415xx/17xx(RCC)
7.1

Reset

There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
7.1.1

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power management reset (see
Software reset
The reset source can be identified by checking the reset flags in the
status register
The SYSRESETREQ bit in Cortex
Register must be set to force a software reset on the device. Refer to the Cortex
FPU technical reference manual for more details.
(RCC_CSR).
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Software reset)
Low-power management
Figure 20).
reset)
RCC clock control &
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