Figure 273. Lsb Justified 16-Bit Or 32-Bit Full-Accuracy With Cpol = 0; Figure 274. Lsb Justified 24-Bit Frame Length With Cpol = 0; Figure 275. Operations Required To Transmit 0X3478Ae - ST STM32F405 Reference Manual

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In transmission mode:

If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register

are required from software or by DMA. The operations are shown below.

In reception mode:

If data 0x3478AE are received, two successive read operations from SPI_DR are

required on each RXNE event.

Figure 273. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0

Transmission

16- or 32-bit data

Channel left

First write to Data register

conditioned by TXE=1

Only the 8 LSB of the

half-word are significant.

A field of 0x00 is forced

instead of the 8 MSBs.

Channel right

Transmission

24-bit remaining

Channel left 32-bit

Second write to Data register

RM0090 Rev 18

Serial peripheral interface (SPI)

Channel right

conditioned by TXE=1

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