ST STM32F405 Reference Manual page 303

RM0090
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Each stream can be configured by hardware to be:
–
–
• Each of the 8 streams are connected to dedicated hardware DMA channels (requests)
•
Priorities between DMA stream requests are software-programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request 0
has priority over request 1, etc.)
•
Each stream also supports software trigger for memory-to-memory transfers (only
available for the DMA2 controller)
• Each stream request can be selected among up to 8 possible channel requests. This
selection is software-configurable and allows several peripherals to initiate DMA
requests
•
The number of data items to be transferred can be managed either by the DMA
controller or by the peripheral:
–
–
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Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
•
Incrementing or non-incrementing addressing for source and destination
•
Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
•
Each stream supports circular buffer management
•
5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA
FIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for
each stream
FIFO to ensure an immediate data transfer as soon as a DMA request is triggered
by a peripheral.
a regular channel that supports peripheral-to-memory, memory-to-peripheral and
memory-to-memory transfers
a double buffer channel that also supports double buffering on the memory side
DMA flow controller: the number of data items to be transferred is software-
programmable from 1 to 65535
Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
RM0090 Rev 18
DMA controller (DMA)
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