ST STM32F405 Reference Manual page 249

RM0090 Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bit 14 SYSCFGEN: System configuration controller clock enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable
Bit 11 SDIOEN: SDIO clock enable
Bit 10 ADC3EN: ADC3 clock enable
Bit 9
Bit 8
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
Bit 4 USART1EN: USART1 clock enable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 clock enable
Bit 0 TIM1EN: TIM1 clock enable
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Set and cleared by software.
0: SDIO module clock disabled
1: SDIO module clock enabled
Set and cleared by software.
0: ADC3 clock disabled
1: ADC3 clock disabled
ADC2EN: ADC2 clock enable
Set and cleared by software.
0: ADC2 clock disabled
1: ADC2 clock disabled
ADC1EN: ADC1 clock enable
Set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock disabled
Set and cleared by software.
0: USART6 clock disabled
1: USART6 clock enabled
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Set and cleared by software.
0: TIM8 clock disabled
1: TIM8 clock enabled
Set and cleared by software.
0: TIM1 clock disabled
1: TIM1 clock enabled
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