ST STM32F405 Reference Manual page 922

Serial peripheral interface (SPI)
28.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I
Address offset: 0x18
Reset value: 0x0000
15 14 13
r r r
Bits 15:0 TXCRC[15:0]: Tx CRC register
Note: A read to this register when the BSY flag is set could return an incorrect value.
2
28.5.8 SPI_I S configuration register (SPI_I2SCFGR)
Address offset: 0x1C
Reset value: 0x0000
15 14 13 12
Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI or I
Bit 10 I2SE: I2S Enable
2
0: I S peripheral is disabled
2
1: I S peripheral is enabled
Note: This bit is not used in SPI mode.
Bits 9:8 I2SCFG: I2S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Note: This bit should be configured when the I
It is not used in SPI mode.
922/1749
12 11 10 9
r r r r
When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1
is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF
bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected
(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16
standard.
These bits are not used for I
11 10 9
I2SMOD I2SE I2SCFG
rw
rw rw
8 7 6
TXCRC[15:0]
r r r
2
S mode.
8 7 6
PCMSY
NC
Res.
rw rw
2
S is disabled
2
S is disabled.
RM0090 Rev 18
2
S mode)
5 4 3 2
r r r r
5 4 3 2
I2SSTD CKPOL DATLEN
rw rw rw rw
RM0090
1 0
r r
1 0
CHLEN
rw rw