Pwr Power Control/Status Register (Pwr_Csr); For Stm32F405Xx/07Xx And Stm32F415Xx/17Xx - ST STM32F405 Reference Manual

Power controller (PWR)
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
5.4.2

PWR power control/status register (PWR_CSR)

for STM32F405xx/07xx and STM32F415xx/17xx

Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31 30 29
15 14 13
VOS
RDY
Res
r
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
142/1749
0: PVD disabled
1: PVD enabled
0: No effect
1: Clear the SBF Standby Flag (write).
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
0: Voltage regulator on during Stop mode
1: Voltage regulator in low-power mode during Stop mode
28 27 26 25
12 11 10 9
BRE
Reserved
rw
0: Not ready
1: Ready
24 23 22
Reserved
8 7 6
EWUP
Reserved
rw
RM0090 Rev 18
21 20 19 18
5 4 3 2
BRR PVDO
r r
RM0090
17 16
1 0
SBF WUF
r r